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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 13:52:24 -04:00
parent 94e4f056db
commit 1a2823da0d
31 changed files with 253 additions and 260 deletions
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8
hw/rtl/Vortex.v
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@@ -43,7 +43,7 @@ module Vortex #(
input wire [31:0] llc_snp_req_addr,
output wire llc_snp_req_ready,
output wire out_ebreak
output wire ebreak
);
`DEBUG_BEGIN
wire scheduler_empty;
@@ -156,7 +156,7 @@ VX_front_end front_end (
.icache_req_if (icache_req_if),
.jal_rsp_if (jal_rsp_if),
.branch_rsp_if (branch_rsp_if),
.fetch_ebreak (out_ebreak)
.fetch_ebreak (ebreak)
);
VX_scheduler schedule (
@@ -184,8 +184,8 @@ VX_back_end #(
.dcache_rsp_if (dcache_rsp_if),
.dcache_req_if (dcache_req_if),
.writeback_if (writeback_if),
.out_mem_delay (memory_delay),
.out_exec_delay (exec_delay),
.mem_delay_o (memory_delay),
.exec_delay_o (exec_delay),
.gpr_stage_delay (gpr_stage_delay)
);