RTL code refactoring

2020-04-20 13:52:24 -04:00
parent 94e4f056db
commit 1a2823da0d
31 changed files with 253 additions and 260 deletions
--- a/hw/modelsim/vortex_tb.v
+++ b/hw/modelsim/vortex_tb.v
@@ -116,7 +116,7 @@ reg[31:0]  io_data;
 		.o_m_read_or_write_i          (o_m_read_or_write_i),
 		.i_m_readdata_i               (i_m_readdata_i),
 		.i_m_ready_i                  (i_m_ready_i),
-		.out_ebreak                   (out_ebreak)
+		.ebreak_o                   (out_ebreak)
 	);

 	always @(negedge clk) begin