fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,
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@@ -7,6 +7,12 @@ namespace vortex {
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class Scoreboard {
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private:
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struct reg_use_t {
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RegType type;
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uint32_t reg;
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uint64_t owner;
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};
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std::vector<RegMask> in_use_iregs_;
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std::vector<RegMask> in_use_fregs_;
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std::vector<RegMask> in_use_vregs_;
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@@ -25,21 +31,21 @@ public:
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}
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}
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bool in_use(const pipeline_state_t& state) const {
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return (state.used_iregs & in_use_iregs_.at(state.wid)) != 0
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|| (state.used_fregs & in_use_fregs_.at(state.wid)) != 0
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|| (state.used_vregs & in_use_vregs_.at(state.wid)) != 0;
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bool in_use(pipeline_trace_t* state) const {
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return (state->used_iregs & in_use_iregs_.at(state->wid)) != 0
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|| (state->used_fregs & in_use_fregs_.at(state->wid)) != 0
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|| (state->used_vregs & in_use_vregs_.at(state->wid)) != 0;
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}
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std::vector<uint64_t> owners(const pipeline_state_t& state) const {
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std::vector<uint64_t> out;
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std::vector<reg_use_t> get_uses(pipeline_trace_t* state) const {
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std::vector<reg_use_t> out;
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{
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uint32_t r = 0;
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auto used_iregs = state.used_iregs & in_use_iregs_.at(state.wid);
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auto used_iregs = state->used_iregs & in_use_iregs_.at(state->wid);
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while (used_iregs.any()) {
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if (used_iregs.test(0)) {
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uint32_t tag = (r << 16) | (state.wid << 4) | (int)RegType::Integer;
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out.push_back(owners_.at(tag));
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uint32_t tag = (r << 16) | (state->wid << 4) | (int)RegType::Integer;
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out.push_back({RegType::Integer, r, owners_.at(tag)});
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}
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used_iregs >>= 1;
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++r;
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@@ -47,11 +53,11 @@ public:
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}
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{
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uint32_t r = 0;
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auto used_fregs = state.used_fregs & in_use_fregs_.at(state.wid);
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auto used_fregs = state->used_fregs & in_use_fregs_.at(state->wid);
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while (used_fregs.any()) {
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if (used_fregs.test(0)) {
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uint32_t tag = (r << 16) | (state.wid << 4) | (int)RegType::Float;
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out.push_back(owners_.at(tag));
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uint32_t tag = (r << 16) | (state->wid << 4) | (int)RegType::Float;
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out.push_back({RegType::Float, r, owners_.at(tag)});
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}
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used_fregs >>= 1;
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++r;
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@@ -59,11 +65,11 @@ public:
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}
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{
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uint32_t r = 0;
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auto used_vregs = state.used_vregs & in_use_vregs_.at(state.wid);
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auto used_vregs = state->used_vregs & in_use_vregs_.at(state->wid);
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while (used_vregs.any()) {
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if (used_vregs.test(0)) {
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uint32_t tag = (r << 16) | (state.wid << 4) | (int)RegType::Vector;
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out.push_back(owners_.at(tag));
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uint32_t tag = (r << 16) | (state->wid << 4) | (int)RegType::Vector;
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out.push_back({RegType::Vector, r, owners_.at(tag)});
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}
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used_vregs >>= 1;
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++r;
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@@ -72,44 +78,44 @@ public:
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return std::move(out);
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}
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void reserve(const pipeline_state_t& state) {
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if (!state.wb)
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void reserve(pipeline_trace_t* state) {
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if (!state->wb)
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return;
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switch (state.rdest_type) {
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switch (state->rdest_type) {
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case RegType::Integer:
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in_use_iregs_.at(state.wid).set(state.rdest);
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in_use_iregs_.at(state->wid).set(state->rdest);
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break;
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case RegType::Float:
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in_use_fregs_.at(state.wid).set(state.rdest);
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in_use_fregs_.at(state->wid).set(state->rdest);
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break;
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case RegType::Vector:
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in_use_vregs_.at(state.wid).set(state.rdest);
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in_use_vregs_.at(state->wid).set(state->rdest);
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break;
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default:
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break;
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}
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uint32_t tag = (state.rdest << 16) | (state.wid << 4) | (int)state.rdest_type;
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uint32_t tag = (state->rdest << 16) | (state->wid << 4) | (int)state->rdest_type;
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assert(owners_.count(tag) == 0);
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owners_[tag] = state.id;
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owners_[tag] = state->id;
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}
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void release(const pipeline_state_t& state) {
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if (!state.wb)
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void release(pipeline_trace_t* state) {
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if (!state->wb)
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return;
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switch (state.rdest_type) {
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switch (state->rdest_type) {
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case RegType::Integer:
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in_use_iregs_.at(state.wid).reset(state.rdest);
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in_use_iregs_.at(state->wid).reset(state->rdest);
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break;
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case RegType::Float:
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in_use_fregs_.at(state.wid).reset(state.rdest);
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in_use_fregs_.at(state->wid).reset(state->rdest);
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break;
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case RegType::Vector:
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in_use_vregs_.at(state.wid).reset(state.rdest);
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in_use_vregs_.at(state->wid).reset(state->rdest);
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break;
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default:
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break;
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}
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uint32_t tag = (state.rdest << 16) | (state.wid << 4) | (int)state.rdest_type;
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uint32_t tag = (state->rdest << 16) | (state->wid << 4) | (int)state->rdest_type;
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owners_.erase(tag);
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}
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};
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