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fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,

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Blaise Tine
2021-11-24 00:00:17 -05:00
parent 1501360f4b
commit 18762dffce
70 changed files with 3818 additions and 1727 deletions
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10
sim/simX/processor.cpp
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@@ -33,7 +33,8 @@ Processor::Processor(const ArchDef& arch)
L3_NUM_BANKS, // number of banks
L3_NUM_PORTS, // number of ports
NUM_CLUSTERS, // request size
true, // write-throught
true, // write-through
false, // write response
0, // victim size
L3_MSHR_SIZE, // mshr
2, // pipeline latency
@@ -74,7 +75,8 @@ Processor::Processor(const ArchDef& arch)
L2_NUM_BANKS, // number of banks
L2_NUM_PORTS, // number of ports
NUM_CORES, // request size
true, // write-throught
true, // write-through
false, // write response
0, // victim size
L2_MSHR_SIZE, // mshr
2, // pipeline latency
@@ -129,7 +131,7 @@ int Processor::run() {
if (core->running()) {
running = true;
}
if (core->check_ebreak()) {
if (core->check_exit()) {
exitcode = core->getIRegValue(3);
running = false;
break;
@@ -137,5 +139,7 @@ int Processor::run() {
}
} while (running);
std::cout << std::flush;
return exitcode;
}