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AXI memory bus support

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This commit is contained in:
Blaise Tine
2021-09-10 01:36:01 -07:00
parent ca46b0a0be
commit 18172fa611
6 changed files with 425 additions and 10 deletions
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191
hw/simulate/simulator.cpp
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@@ -66,7 +66,12 @@ Simulator::Simulator() {
Verilated::assertOn(false);
ram_ = nullptr;
#ifdef AXI_BUS
vortex_ = new VVortex_axi();
#else
vortex_ = new VVortex();
#endif
#ifdef VCD_OUTPUT
Verilated::traceEverOn(true);
@@ -103,15 +108,18 @@ void Simulator::attach_ram(RAM* ram) {
void Simulator::reset() {
print_bufs_.clear();
for (int b = 0; b < MEMORY_BANKS; ++b) {
mem_rsp_vec_[b].clear();
}
last_mem_rsp_bank_ = 0;
mem_rsp_active_ = false;
vortex_->mem_rsp_valid = 0;
vortex_->mem_req_ready = 0;
#ifdef AXI_BUS
this->reset_axi_bus();
#else
this->reset_mem_bus();
#endif
vortex_->reset = 1;
@@ -133,12 +141,20 @@ void Simulator::step() {
vortex_->clk = 0;
this->eval();
mem_rsp_ready_ = vortex_->mem_rsp_ready;
#ifdef AXI_BUS
this->eval_axi_bus(0);
#else
this->eval_mem_bus(0);
#endif
vortex_->clk = 1;
this->eval();
this->eval_mem_bus();
#ifdef AXI_BUS
this->eval_axi_bus(1);
#else
this->eval_mem_bus(1);
#endif
#ifndef NDEBUG
fflush(stdout);
@@ -155,7 +171,158 @@ void Simulator::eval() {
++timestamp;
}
void Simulator::eval_mem_bus() {
#ifdef AXI_BUS
void Simulator::reset_axi_bus() {
vortex_->m_axi_wready = 0;
vortex_->m_axi_awready = 0;
vortex_->m_axi_arready = 0;
vortex_->m_axi_rvalid = 0;
}
void Simulator::eval_axi_bus(bool clk) {
if (!clk) {
mem_rsp_ready_ = vortex_->m_axi_rready;
return;
}
if (ram_ == nullptr) {
vortex_->m_axi_wready = 0;
vortex_->m_axi_awready = 0;
vortex_->m_axi_arready = 0;
return;
}
// update memory responses schedule
for (int b = 0; b < MEMORY_BANKS; ++b) {
for (auto& rsp : mem_rsp_vec_[b]) {
if (rsp.cycles_left > 0)
rsp.cycles_left -= 1;
}
}
bool has_response = false;
// schedule memory responses that are ready
for (int i = 0; i < MEMORY_BANKS; ++i) {
uint32_t b = (i + last_mem_rsp_bank_ + 1) % MEMORY_BANKS;
if (!mem_rsp_vec_[b].empty()
&& (mem_rsp_vec_[b].begin()->cycles_left) <= 0) {
has_response = true;
last_mem_rsp_bank_ = b;
break;
}
}
// send memory response
if (mem_rsp_active_
&& vortex_->m_axi_rvalid && mem_rsp_ready_) {
mem_rsp_active_ = false;
}
if (!mem_rsp_active_) {
if (has_response) {
vortex_->m_axi_rvalid = 1;
std::list<mem_req_t>::iterator mem_rsp_it = mem_rsp_vec_[last_mem_rsp_bank_].begin();
/*
printf("%0ld: [sim] MEM Rd: bank=%d, addr=%0lx, data=", timestamp, last_mem_rsp_bank_, mem_rsp_it->addr);
for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
printf("%02x", mem_rsp_it->block[(MEM_BLOCK_SIZE-1)-i]);
}
printf("\n");
*/
memcpy((uint8_t*)vortex_->m_axi_rdata, mem_rsp_it->block.data(), MEM_BLOCK_SIZE);
vortex_->m_axi_rid = mem_rsp_it->tag;
mem_rsp_vec_[last_mem_rsp_bank_].erase(mem_rsp_it);
mem_rsp_active_ = true;
} else {
vortex_->m_axi_rvalid = 0;
}
}
// select the memory bank
uint32_t req_addr = vortex_->m_axi_wvalid ? vortex_->m_axi_awaddr : vortex_->m_axi_araddr;
uint32_t req_bank = (MEMORY_BANKS >= 2) ? ((req_addr / MEM_BLOCK_SIZE) % MEMORY_BANKS) : 0;
// handle memory stalls
bool mem_stalled = false;
#ifdef ENABLE_MEM_STALLS
if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) {
mem_stalled = true;
} else
if (mem_rsp_vec_[req_bank].size() >= MEM_RQ_SIZE) {
mem_stalled = true;
}
#endif
// process memory requests
if (!mem_stalled) {
if (vortex_->m_axi_wvalid || vortex_->m_axi_arvalid) {
if (vortex_->m_axi_wvalid) {
uint64_t byteen = vortex_->m_axi_wstrb;
unsigned base_addr = vortex_->m_axi_awaddr;
uint8_t* data = (uint8_t*)(vortex_->m_axi_wdata);
if (base_addr >= IO_COUT_ADDR
&& base_addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) {
for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
if ((byteen >> i) & 0x1) {
auto& ss_buf = print_bufs_[i];
char c = data[i];
ss_buf << c;
if (c == '\n') {
std::cout << std::dec << "#" << i << ": " << ss_buf.str() << std::flush;
ss_buf.str("");
}
}
}
} else {
/*
printf("%0ld: [sim] MEM Wr: addr=%0x, byteen=%0lx, data=", timestamp, base_addr, byteen);
for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
printf("%02x", data[(MEM_BLOCK_SIZE-1)-i]);
}
printf("\n");
*/
for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
if ((byteen >> i) & 0x1) {
(*ram_)[base_addr + i] = data[i];
}
}
}
} else {
mem_req_t mem_req;
mem_req.tag = vortex_->m_axi_arid;
mem_req.addr = vortex_->m_axi_araddr;
ram_->read(vortex_->m_axi_araddr, MEM_BLOCK_SIZE, mem_req.block.data());
mem_req.cycles_left = MEM_LATENCY;
for (auto& rsp : mem_rsp_vec_[req_bank]) {
if (mem_req.addr == rsp.addr) {
// duplicate requests receive the same cycle delay
mem_req.cycles_left = rsp.cycles_left;
break;
}
}
mem_rsp_vec_[req_bank].emplace_back(mem_req);
}
}
}
vortex_->m_axi_wready = !mem_stalled;
vortex_->m_axi_awready = !mem_stalled;
vortex_->m_axi_arready = !mem_stalled;
}
#else
void Simulator::reset_mem_bus() {
vortex_->mem_req_ready = 0;
vortex_->mem_rsp_valid = 0;
}
void Simulator::eval_mem_bus(bool clk) {
if (!clk) {
mem_rsp_ready_ = vortex_->mem_rsp_ready;
return;
}
if (ram_ == nullptr) {
vortex_->mem_req_ready = 0;
return;
@@ -276,6 +443,8 @@ void Simulator::eval_mem_bus() {
vortex_->mem_req_ready = !mem_stalled;
}
#endif
void Simulator::wait(uint32_t cycles) {
for (int i = 0; i < cycles; ++i) {
this->step();
@@ -309,11 +478,19 @@ int Simulator::run() {
}
bool Simulator::get_ebreak() const {
#ifdef AXI_BUS
return (int)vortex_->Vortex_axi->vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak;
#else
return (int)vortex_->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak;
#endif
}
int Simulator::get_last_wb_value(int reg) const {
#ifdef AXI_BUS
return (int)vortex_->Vortex_axi->vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
#else
return (int)vortex_->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
#endif
}
void Simulator::load_bin(const char* program_file) {