L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00
parent a7da36c007
commit 1795980a52
50 changed files with 972 additions and 952 deletions
--- a/hw/rtl/interfaces/VX_wstall_if.v
+++ b/hw/rtl/interfaces/VX_wstall_if.v
@@ -5,7 +5,7 @@

 interface VX_wstall_if();

-    wire                valid;
+    wire                valid;    
    wire [`NW_BITS-1:0]	wid;

 endinterface