L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00
parent a7da36c007
commit 1795980a52
50 changed files with 972 additions and 952 deletions
--- a/hw/rtl/interfaces/VX_writeback_if.v
+++ b/hw/rtl/interfaces/VX_writeback_if.v
@@ -6,13 +6,12 @@
 interface VX_writeback_if ();

    wire                            valid;
+
    wire [`NUM_THREADS-1:0]         tmask;
    wire [`NW_BITS-1:0]             wid; 
-
 `IGNORE_WARNINGS_BEGIN
    wire [31:0]                     PC;
 `IGNORE_WARNINGS_END
-
    wire [`NR_BITS-1:0]             rd;
    wire [`NUM_THREADS-1:0][31:0]	data;