L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00
parent a7da36c007
commit 1795980a52
50 changed files with 972 additions and 952 deletions
--- a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v
+++ b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v
@@ -9,8 +9,10 @@ interface VX_cache_dram_rsp_if #(
 ) ();

    wire                        valid;
+    
    wire [DRAM_LINE_WIDTH-1:0]  data;
    wire [DRAM_TAG_WIDTH-1:0]   tag;  
+
    wire                        ready;      

 endinterface