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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

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Blaise Tine
2020-11-21 09:47:56 -08:00
parent a7da36c007
commit 1795980a52
50 changed files with 972 additions and 952 deletions
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6
driver/rtlsim/Makefile
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@@ -1,5 +1,5 @@
CFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors
#CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
#CFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors
CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
CFLAGS += -I../../include -I../../../hw/simulate -I../../../hw
@@ -65,7 +65,7 @@ else
endif
# use DPI FPU
#VL_FLAGS += -DFPU_FAST
VL_FLAGS += -DFPU_FAST
PROJECT = libvortex.so
# PROJECT = libvortex.dylib