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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

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Blaise Tine
2020-11-21 09:47:56 -08:00
parent a7da36c007
commit 1795980a52
50 changed files with 972 additions and 952 deletions
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8
driver/opae/vlsim/Makefile
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@@ -1,5 +1,5 @@
CFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors
#CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
#CFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors
CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
CFLAGS += -I../../../../hw
@@ -30,7 +30,7 @@ CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
CFLAGS += -fPIC
CFLAGS += -DUSE_RTLSIM $(CONFIGS)
CFLAGS += -DUSE_VLSIM $(CONFIGS)
CFLAGS += -DDUMP_PERF_STATS
@@ -79,7 +79,7 @@ VL_FLAGS += -DNOPAE
CFLAGS += -DNOPAE
# use DPI FPU
#VL_FLAGS += -DFPU_FAST
VL_FLAGS += -DFPU_FAST
RTL_INCLUDE += -I../../../hw/opae -I../../../hw/opae/ccip