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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

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Blaise Tine
2020-11-21 09:47:56 -08:00
parent a7da36c007
commit 1795980a52
50 changed files with 972 additions and 952 deletions
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.travis.yml
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@@ -20,19 +20,21 @@ install:
- export PATH=$VERILATOR_ROOT/bin:$PATH
script:
- make -j
- ci/test_runtime.sh
- ci/test_driver.sh
- ci/test_riscv_isa.sh
- ci/test_opencl.sh
- ci/blackbox.sh -run_debug
- ci/blackbox.sh -run_scope
- ci/blackbox.sh -run_1c
- ci/blackbox.sh -run_2c
- ci/blackbox.sh -run_4c
- ci/blackbox.sh -run_4c_l2
- travis_wait 30 ci/blackbox.sh -run_4c_2l2_l3
- travis_wait 30 ci/blackbox.sh -run_8c_4l2_l3
- travis_wait 45 make
- travis_wait 45 ci/test_runtime.sh
- travis_wait 45 ci/test_driver.sh
- travis_wait 45 ci/test_riscv_isa.sh
- travis_wait 45 ci/test_opencl.sh
- travis_wait 45 ci/blackbox.sh --driver=rtlsim
- travis_wait 45 ci/blackbox.sh --driver=vlsim
- travis_wait 45 ci/blackbox.sh --driver=vlsim --scope
- travis_wait 45 ci/blackbox.sh --driver=vlsim --debug
- travis_wait 45 ci/blackbox.sh --driver=vlsim --cores=1
- travis_wait 45 ci/blackbox.sh --driver=vlsim --cores=2
- travis_wait 45 ci/blackbox.sh --driver=vlsim --cores=4
- travis_wait 45 ci/blackbox.sh --driver=vlsim --cores=4 --l2cache
- travis_wait 45 ci/blackbox.sh --driver=vlsim --cores=2 --l2cache --clusters=2
- travis_wait 45 ci/blackbox.sh --driver=vlsim --cores=2 --l2cache --clusters=4
after_success:
# Gather code coverage