From a79253329c801b932457b2c1f66aa94853c4422c Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 15 Mar 2021 14:39:55 -0700 Subject: [PATCH] relaxing commit back-pressure in writeback stage --- hw/rtl/VX_writeback.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v index 4dee992f..fb3874e9 100644 --- a/hw/rtl/VX_writeback.v +++ b/hw/rtl/VX_writeback.v @@ -79,10 +79,10 @@ module VX_writeback #( .data_out ({writeback_if.valid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data, writeback_if.eop}) ); - assign ld_commit_if.ready = !stall; - assign fpu_commit_if.ready = !stall && !ld_valid; - assign csr_commit_if.ready = !stall && !ld_valid && !fpu_valid; - assign alu_commit_if.ready = !stall && !ld_valid && !fpu_valid && !csr_valid; + assign ld_commit_if.ready = !(ld_commit_if.wb && (stall)); + assign fpu_commit_if.ready = !(fpu_commit_if.wb && (stall || ld_valid)); + assign csr_commit_if.ready = !(csr_commit_if.wb && (stall || ld_valid || fpu_valid)); + assign alu_commit_if.ready = !(alu_commit_if.wb && (stall || ld_valid || fpu_valid || csr_valid)); // special workaround to get RISC-V tests Pass/Fail status reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */;