From 16f1f24a620337d0877a390e7547764dbf1ffca3 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 2 Aug 2021 20:35:28 -0700 Subject: [PATCH] minor update --- hw/rtl/tex_unit/VX_tex_addr.v | 56 ++++++++++++++++------------------- 1 file changed, 26 insertions(+), 30 deletions(-) diff --git a/hw/rtl/tex_unit/VX_tex_addr.v b/hw/rtl/tex_unit/VX_tex_addr.v index ae939673..fdc6fd42 100644 --- a/hw/rtl/tex_unit/VX_tex_addr.v +++ b/hw/rtl/tex_unit/VX_tex_addr.v @@ -40,12 +40,11 @@ module VX_tex_addr #( wire [NUM_REQS-1:0] tmask_s0; wire [`TEX_FILTER_BITS-1:0] filter_s0; wire [REQ_INFO_WIDTH-1:0] req_info_s0; - wire [NUM_REQS-1:0][1:0][31:0] coord_lo, coord_lo_s0; - wire [NUM_REQS-1:0][1:0][31:0] coord_hi, coord_hi_s0; + wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_lo, clamped_lo_s0; + wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_hi, clamped_hi_s0; wire [`TEX_STRIDE_BITS-1:0] log_stride, log_stride_s0; wire [NUM_REQS-1:0][31:0] mip_addr, mip_addr_s0; wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] log_dims_s0; - wire [1:0][`TEX_WRAP_BITS-1:0] req_wraps_s0; wire stall_out; @@ -62,21 +61,37 @@ module VX_tex_addr #( for (genvar i = 0; i < NUM_REQS; ++i) begin for (genvar j = 0; j < 2; ++j) begin - assign coord_lo[i][j] = req_filter ? (req_coords[j][i] - (`FIXED_HALF >> req_logdims[i][j])) : req_coords[j][i]; - assign coord_hi[i][j] = req_filter ? (req_coords[j][i] + (`FIXED_HALF >> req_logdims[i][j])) : req_coords[j][i]; + wire [31:0] coord_lo = req_filter ? (req_coords[j][i] - (`FIXED_HALF >> req_logdims[i][j])) : req_coords[j][i]; + wire [31:0] coord_hi = req_filter ? (req_coords[j][i] + (`FIXED_HALF >> req_logdims[i][j])) : req_coords[j][i]; + + VX_tex_wrap #( + .CORE_ID (CORE_ID) + ) tex_wrap_lo ( + .wrap_i (req_wraps[j]), + .coord_i (coord_lo), + .coord_o (clamped_lo[i][j]) + ); + + VX_tex_wrap #( + .CORE_ID (CORE_ID) + ) tex_wrap_hi ( + .wrap_i (req_wraps[j]), + .coord_i (coord_hi), + .coord_o (clamped_hi[i][j]) + ); end assign mip_addr[i] = req_baseaddr + 32'(req_mipoff[i]); end VX_pipe_register #( - .DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFO_WIDTH + 2 * `TEX_WRAP_BITS + NUM_REQS * (2 * `TEX_DIM_BITS + 32 + 2 * 2 * 32)), + .DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFO_WIDTH + NUM_REQS * (2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)), .RESETW (1) ) pipe_reg0 ( .clk (clk), .reset (reset), .enable (~stall_out), - .data_in ({req_valid, req_tmask, req_filter, log_stride, req_info, req_wraps, req_logdims, mip_addr, coord_lo, coord_hi}), - .data_out ({valid_s0, tmask_s0, filter_s0, log_stride_s0, req_info_s0, req_wraps_s0, log_dims_s0, mip_addr_s0, coord_lo_s0, coord_hi_s0}) + .data_in ({req_valid, req_tmask, req_filter, log_stride, req_info, req_logdims, mip_addr, clamped_lo, clamped_hi}), + .data_out ({valid_s0, tmask_s0, filter_s0, log_stride_s0, req_info_s0, log_dims_s0, mip_addr_s0, clamped_lo_s0, clamped_hi_s0}) ); // addresses generation @@ -88,28 +103,9 @@ module VX_tex_addr #( for (genvar i = 0; i < NUM_REQS; ++i) begin for (genvar j = 0; j < 2; ++j) begin - wire [`FIXED_FRAC-1:0] clamped_lo; - wire [`FIXED_FRAC-1:0] clamped_hi; - - VX_tex_wrap #( - .CORE_ID (CORE_ID) - ) tex_wrap_lo ( - .wrap_i (req_wraps_s0[j]), - .coord_i (coord_lo_s0[i][j]), - .coord_o (clamped_lo) - ); - - VX_tex_wrap #( - .CORE_ID (CORE_ID) - ) tex_wrap_hi ( - .wrap_i (req_wraps_s0[j]), - .coord_i (coord_hi_s0[i][j]), - .coord_o (clamped_hi) - ); - - assign scaled_lo[i][j] = `FIXED_INT'(clamped_lo >> ((`FIXED_FRAC) - log_dims_s0[i][j])); - assign scaled_hi[i][j] = `FIXED_INT'(clamped_hi >> ((`FIXED_FRAC) - log_dims_s0[i][j])); - assign blends[i][j] = filter_s0 ? clamped_lo[`BLEND_FRAC-1:0] : `BLEND_FRAC'(0); + assign scaled_lo[i][j] = `FIXED_INT'(clamped_lo_s0[i][j] >> ((`FIXED_FRAC) - log_dims_s0[i][j])); + assign scaled_hi[i][j] = `FIXED_INT'(clamped_hi_s0[i][j] >> ((`FIXED_FRAC) - log_dims_s0[i][j])); + assign blends[i][j] = filter_s0 ? clamped_lo_s0[i][j][`BLEND_FRAC-1:0] : `BLEND_FRAC'(0); end end