diff --git a/driver/tests/basic/kernel.bin b/driver/tests/basic/kernel.bin
old mode 100644
new mode 100755
diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh
index b8b3a9b2..85cdc483 100644
--- a/hw/rtl/VX_define.vh
+++ b/hw/rtl/VX_define.vh
@@ -397,8 +397,16 @@
 
     `define SCOPE_ASSIGN(d,s) assign d = s
 `else
-    `define SCOPE_SIGNALS_IO
-    `define SCOPE_SIGNALS_ATTACH
+    `define SCOPE_SIGNALS_ICACHE_IO
+    `define SCOPE_SIGNALS_DCACHE_IO
+    `define SCOPE_SIGNALS_DRAM_IO
+    `define SCOPE_SIGNALS_CORE_IO
+
+    `define SCOPE_SIGNALS_ICACHE_ATTACH
+    `define SCOPE_SIGNALS_DCACHE_ATTACH
+    `define SCOPE_SIGNALS_DRAM_ATTACH
+    `define SCOPE_SIGNALS_CORE_ATTACH
+    
     `define SCOPE_ASSIGN(d,s)
 `endif
 
diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp
index 9c70faeb..18fdb968 100644
--- a/hw/simulate/simulator.cpp
+++ b/hw/simulate/simulator.cpp
@@ -233,12 +233,12 @@ bool Simulator::run() {
 
   // check riscv-tests PASSED/FAILED status
 #if (NUM_CLUSTERS == 1 && NUM_CORES == 1)
-  int status = (int)vortex_->Vortex_Socket->genblk1__DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->back_end->writeback->last_data_wb & 0xf;
+  int status = (int)vortex_->Vortex_Socket->genblk1__DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->pipeline->back_end->writeback->last_data_wb & 0xf;
 #else
 #if (NUM_CLUSTERS == 1)
-  int status = (int)vortex_->Vortex_Socket->genblk1__DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->back_end->writeback->last_data_wb & 0xf;
+  int status = (int)vortex_->Vortex_Socket->genblk1__DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->pipeline->back_end->writeback->last_data_wb & 0xf;
 #else
-  int status = (int)vortex_->Vortex_Socket->genblk2__DOT__genblk1__BRA__0__KET____DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->back_end->writeback->last_data_wb & 0xf;
+  int status = (int)vortex_->Vortex_Socket->genblk2__DOT__genblk1__BRA__0__KET____DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->pipeline->back_end->writeback->last_data_wb & 0xf;
 #endif
 #endif