diff --git a/hw/rtl/cache/VX_Cache_Bank.v b/hw/rtl/cache/VX_Cache_Bank.v index aaf33954..68c681c2 100644 --- a/hw/rtl/cache/VX_Cache_Bank.v +++ b/hw/rtl/cache/VX_Cache_Bank.v @@ -67,7 +67,7 @@ module VX_Cache_Bank localparam RECIV_MEM_RSP = 2; - localparam BLOCK_NUM_BITS = `LOG2UP(CACHE_BLOCK); + localparam BLOCK_BITS = `LOG2UP(CACHE_BLOCK); // Inputs input wire rst; input wire clk; @@ -134,9 +134,7 @@ module VX_Cache_Bank assign write_from_mem = (state == RECIV_MEM_RSP) && valid_in; // TODO assign hit = (access && (tag_use == o_tag) && valid_use); //assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data - assign eviction_addr = {eviction_tag, actual_index, {(BLOCK_NUM_BITS){1'b0}}}; // Fix with actual data - - + assign eviction_addr = {eviction_tag, actual_index, {(BLOCK_BITS){1'b0}}}; // Fix with actual data wire lw = (i_p_mem_read == `LW_MEM_READ); wire lb = (i_p_mem_read == `LB_MEM_READ); @@ -158,14 +156,12 @@ module VX_Cache_Bank b2 ? (data_use[block_offset] >> 16) : (data_use[block_offset] >> 24); - wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF); wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF); wire[31:0] lbu_data = (data_unQual & 32'hFF); wire[31:0] lhu_data = (data_unQual & 32'hFFFF); wire[31:0] lw_data = (data_unQual); - wire[31:0] sw_data = writedata; wire[31:0] sb_data = b1 ? {{16{1'b0}}, writedata[7:0], { 8{1'b0}}} : @@ -175,8 +171,6 @@ module VX_Cache_Bank wire[31:0] sh_data = b2 ? {writedata[15:0], {16{1'b0}}} : writedata; - - wire[31:0] use_write_data = sb ? sb_data : sh ? sh_data : sw_data; @@ -188,14 +182,11 @@ module VX_Cache_Bank lbu ? lbu_data : lw_data; - assign readdata = (access) ? data_Qual : 32'b0; // Fix with actual data - wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000))); wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); - wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we; wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write; genvar g; @@ -209,14 +200,12 @@ module VX_Cache_Bank (normal_write && sh) ? sh_mask : 4'b0000; - // assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0; assign data_write[g] = write_from_mem ? fetched_writedata[g] : use_write_data; assign way_to_update = evicted_way; end endgenerate - VX_cache_data_per_index #( .CACHE_WAYS (CACHE_WAYS), .NUM_IND (NUM_IND), @@ -244,8 +233,6 @@ module VX_Cache_Bank .dirty_use (dirty_use) ); - - endmodule diff --git a/hw/rtl/generic_cache/VX_bank.v b/hw/rtl/generic_cache/VX_bank.v index 63817263..0212ded7 100644 --- a/hw/rtl/generic_cache/VX_bank.v +++ b/hw/rtl/generic_cache/VX_bank.v @@ -410,13 +410,12 @@ module VX_bank #( end endgenerate - - wire[`WORD_SIZE_RNG] readword_st1e; + wire[`WORD_SIZE_RNG] readword_st1e; wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] readdata_st1e; - wire[`TAG_SELECT_SIZE_RNG] readtag_st1e; - wire miss_st1e; - wire dirty_st1e; - wire[31:0] pc_st1e; + wire[`TAG_SELECT_BITS-1:0] readtag_st1e; + wire miss_st1e; + wire dirty_st1e; + wire[31:0] pc_st1e; `DEBUG_BEGIN wire [4:0] rd_st1e; wire [1:0] wb_st1e; @@ -489,13 +488,13 @@ module VX_bank #( wire miss_st2; wire dirty_st2; wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2; - wire[`TAG_SELECT_SIZE_RNG] readtag_st2; + wire[`TAG_SELECT_BITS-1:0] readtag_st2; wire fill_saw_dirty_st2; wire is_snp_st2; wire [31:0] pc_st2; VX_generic_register #( - .N( 1+1+1+1+32+`WORD_SIZE+`WORD_SIZE+(`BANK_LINE_WORDS * `WORD_SIZE) + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS + 32 + 2) + .N( 1+1+1+1+32+`WORD_SIZE+`WORD_SIZE+(`BANK_LINE_WORDS * `WORD_SIZE) + `REQ_INST_META_SIZE + `TAG_SELECT_BITS + 32 + 2) ) st_1e_2 ( .clk (clk), .reset(reset), diff --git a/hw/rtl/generic_cache/VX_cache_config.vh b/hw/rtl/generic_cache/VX_cache_config.vh index 4500a5f6..fa0cf39e 100644 --- a/hw/rtl/generic_cache/VX_cache_config.vh +++ b/hw/rtl/generic_cache/VX_cache_config.vh @@ -3,25 +3,25 @@ `include "../VX_define.vh" -// data tid rd wb warp_num read write -`define MRVQ_METADATA_SIZE (`WORD_SIZE + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1 + 1) + 3 + 3) +// data tid rd wb warp_num read write +`define MRVQ_METADATA_SIZE (`WORD_SIZE + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS) + 3 + 3) -// 5 + 2 + 4 + 3 + 3 + 1 -`define REQ_INST_META_SIZE (5 + 2 + (`NW_BITS-1+1) + 3 + 3 + `LOG2UP(NUM_REQUESTS)) +// rd wb warp_num read write + reqs +`define REQ_INST_META_SIZE (5 + 2 + (`NW_BITS) + 3 + 3 + `LOG2UP(NUM_REQUESTS)) -`define WORD_SIZE (8 * WORD_SIZE_BYTES) -`define WORD_SIZE_RNG (`WORD_SIZE)-1:0 +`define WORD_SIZE (8 * WORD_SIZE_BYTES) +`define WORD_SIZE_RNG (`WORD_SIZE)-1:0 // 128 -`define BANK_SIZE_BYTES (CACHE_SIZE_BYTES / NUM_BANKS) +`define BANK_SIZE_BYTES (CACHE_SIZE_BYTES / NUM_BANKS) // 8 -`define BANK_LINE_COUNT (`BANK_SIZE_BYTES / BANK_LINE_SIZE_BYTES) +`define BANK_LINE_COUNT (`BANK_SIZE_BYTES / BANK_LINE_SIZE_BYTES) // 4 -`define BANK_LINE_WORDS (BANK_LINE_SIZE_BYTES / WORD_SIZE_BYTES) +`define BANK_LINE_WORDS (BANK_LINE_SIZE_BYTES / WORD_SIZE_BYTES) // Offset is fixed -`define OFFSET_ADDR_NUM_BITS 2 +`define OFFSET_ADDR_BITS 2 `define OFFSET_SIZE_END 1 `define OFFSET_ADDR_START 0 `define OFFSET_ADDR_END 1 @@ -29,54 +29,45 @@ `define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0 // 2 -`define WORD_SELECT_NUM_BITS (`LOG2UP(`BANK_LINE_WORDS)) +`define WORD_SELECT_BITS (`LOG2UP(`BANK_LINE_WORDS)) // 2 -`define WORD_SELECT_SIZE_END (`WORD_SELECT_NUM_BITS) +`define WORD_SELECT_SIZE_END (`WORD_SELECT_BITS) // 2 -`define WORD_SELECT_ADDR_START (1+`OFFSET_ADDR_END) +`define WORD_SELECT_ADDR_START (1+`OFFSET_ADDR_END) // 3 -`define WORD_SELECT_ADDR_END (`WORD_SELECT_SIZE_END+`OFFSET_ADDR_END) +`define WORD_SELECT_ADDR_END (`WORD_SELECT_SIZE_END+`OFFSET_ADDR_END) // 3:2 -`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START -`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:0 +`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START // 3 -`define BANK_SELECT_NUM_BITS (`LOG2UP(NUM_BANKS)) +`define BANK_SELECT_BITS (`LOG2UP(NUM_BANKS)) // 3 -`define BANK_SELECT_SIZE_END (`BANK_SELECT_NUM_BITS) +`define BANK_SELECT_SIZE_END (`BANK_SELECT_BITS) // 4 -`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END) +`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END) // 6 -`define BANK_SELECT_ADDR_END (`BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START-1) +`define BANK_SELECT_ADDR_END (`BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START-1) // 6:4 -`define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START -// 2:0 -`define BANK_SELECT_SIZE_RNG `BANK_SELECT_SIZE_END-1:0 +`define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START // 3 -`define LINE_SELECT_NUM_BITS (`LOG2UP(`BANK_LINE_COUNT)) +`define LINE_SELECT_BITS (`LOG2UP(`BANK_LINE_COUNT)) // 7 -`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END) +`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END) // 9 -`define LINE_SELECT_ADDR_END (`LINE_SELECT_NUM_BITS+`LINE_SELECT_ADDR_START-1) +`define LINE_SELECT_ADDR_END (`LINE_SELECT_BITS+`LINE_SELECT_ADDR_START-1) // 9:7 -`define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START -// 2:0 -`define LINE_SELECT_SIZE_RNG `LINE_SELECT_NUM_BITS-1:0 +`define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START // 10 -`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END) +`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END) // 31:10 -`define TAG_SELECT_ADDR_RNG 31:`TAG_SELECT_ADDR_START +`define TAG_SELECT_ADDR_RNG 31:`TAG_SELECT_ADDR_START // 22 -`define TAG_SELECT_NUM_BITS (32-`TAG_SELECT_ADDR_START) -// 22 -`define TAG_SELECT_SIZE_END (`TAG_SELECT_NUM_BITS) -// 21:0 -`define TAG_SELECT_SIZE_RNG `TAG_SELECT_NUM_BITS-1:0 +`define TAG_SELECT_BITS (32-`TAG_SELECT_ADDR_START) -`define TAG_LINE_SELECT_BITS (`TAG_SELECT_NUM_BITS+`LINE_SELECT_NUM_BITS) +`define TAG_LINE_SELECT_BITS (`TAG_SELECT_BITS+`LINE_SELECT_BITS) -`define BASE_ADDR_MASK (~((1<<(`WORD_SELECT_ADDR_END+1))-1)) +`define BASE_ADDR_MASK (~((1<<(`WORD_SELECT_ADDR_END+1))-1)) `endif diff --git a/hw/rtl/generic_cache/VX_tag_data_access.v b/hw/rtl/generic_cache/VX_tag_data_access.v index 5d0dd4e4..50a745fd 100644 --- a/hw/rtl/generic_cache/VX_tag_data_access.v +++ b/hw/rtl/generic_cache/VX_tag_data_access.v @@ -62,7 +62,7 @@ module VX_tag_data_access #( output wire[`WORD_SIZE_RNG] readword_st1e, output wire[`DBANK_LINE_WORDS-1:0][31:0] readdata_st1e, - output wire[`TAG_SELECT_SIZE_RNG] readtag_st1e, + output wire[`TAG_SELECT_BITS-1:0] readtag_st1e, output wire miss_st1e, output wire dirty_st1e, output wire fill_saw_dirty_st1e @@ -70,17 +70,17 @@ module VX_tag_data_access #( reg read_valid_st1c[STAGE_1_CYCLES-1:0]; reg read_dirty_st1c[STAGE_1_CYCLES-1:0]; - reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [STAGE_1_CYCLES-1:0]; + reg[`TAG_SELECT_BITS-1:0] read_tag_st1c [STAGE_1_CYCLES-1:0]; reg[`DBANK_LINE_WORDS-1:0][31:0] read_data_st1c [STAGE_1_CYCLES-1:0]; wire qual_read_valid_st1; wire qual_read_dirty_st1; - wire[`TAG_SELECT_SIZE_RNG] qual_read_tag_st1; + wire[`TAG_SELECT_BITS-1:0] qual_read_tag_st1; wire[`DBANK_LINE_WORDS-1:0][31:0] qual_read_data_st1; wire use_read_valid_st1e; wire use_read_dirty_st1e; - wire[`TAG_SELECT_SIZE_RNG] use_read_tag_st1e; + wire[`TAG_SELECT_BITS-1:0] use_read_tag_st1e; wire[`DBANK_LINE_WORDS-1:0][31:0] use_read_data_st1e; wire[`DBANK_LINE_WORDS-1:0][3:0] use_write_enable; wire[`DBANK_LINE_WORDS-1:0][31:0] use_write_data; @@ -130,9 +130,9 @@ module VX_tag_data_access #( .fill_sent (fill_sent) ); - // VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_WORDS*32) )) s0_1_c0 ( + // VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_BITS + (`DBANK_LINE_WORDS*32) )) s0_1_c0 ( VX_generic_register #( - .N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_WORDS*32) ), + .N( 1 + 1 + `TAG_SELECT_BITS + (`DBANK_LINE_WORDS*32) ), .PassThru(1) ) s0_1_c0 ( .clk (clk), @@ -147,7 +147,7 @@ module VX_tag_data_access #( generate for (curr_stage = 1; curr_stage < STAGE_1_CYCLES-1; curr_stage = curr_stage + 1) begin VX_generic_register #( - .N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_WORDS*32)) + .N( 1 + 1 + `TAG_SELECT_BITS + (`DBANK_LINE_WORDS*32)) ) s0_1_cc ( .clk (clk), .reset(reset), @@ -170,7 +170,7 @@ module VX_tag_data_access #( /////////////////////// LOAD LOGIC /////////////////// wire[`OFFSET_SIZE_RNG] byte_select = writeaddr_st1e[`OFFSET_ADDR_RNG]; - wire[`WORD_SELECT_SIZE_RNG] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG]; + wire[`WORD_SELECT_BITS-1:0] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG]; `IGNORE_WARNINGS_BEGIN wire lw = valid_req_st1e && (mem_read_st1e == `LW_MEM_READ); @@ -210,7 +210,7 @@ module VX_tag_data_access #( genvar g; generate for (g = 0; g < `DBANK_LINE_WORDS; g = g + 1) begin : write_enables - wire normal_write = (block_offset == g[`WORD_SELECT_SIZE_RNG]) && should_write && !real_writefill; + wire normal_write = (block_offset == g[`WORD_SELECT_BITS-1:0]) && should_write && !real_writefill; assign we[g] = (force_write) ? 4'b1111 : (should_write && !real_writefill && (FUNC_ID == `L2FUNC_ID)) ? 4'b1111 : @@ -238,8 +238,6 @@ module VX_tag_data_access #( assign use_write_enable = (writefill_st1e && !real_writefill) ? 0 : we; assign use_write_data = data_write; -/////////////////////// - if (FUNC_ID == `L2FUNC_ID) begin assign readword_st1e = read_data_st1c[STAGE_1_CYCLES-1]; end else begin diff --git a/hw/rtl/generic_cache/VX_tag_data_structure.v b/hw/rtl/generic_cache/VX_tag_data_structure.v index 0fb13742..c4e36d98 100644 --- a/hw/rtl/generic_cache/VX_tag_data_structure.v +++ b/hw/rtl/generic_cache/VX_tag_data_structure.v @@ -46,23 +46,23 @@ module VX_tag_data_structure #( input wire reset, input wire stall_bank_pipe, - input wire[`LINE_SELECT_SIZE_RNG] read_addr, + input wire[`LINE_SELECT_BITS-1:0] read_addr, output wire read_valid, output wire read_dirty, - output wire[`TAG_SELECT_SIZE_RNG] read_tag, + output wire[`TAG_SELECT_BITS-1:0] read_tag, output wire[`DBANK_LINE_WORDS-1:0][31:0] read_data, input wire invalidate, input wire[`DBANK_LINE_WORDS-1:0][3:0] write_enable, input wire write_fill, - input wire[`LINE_SELECT_SIZE_RNG] write_addr, - input wire[`TAG_SELECT_SIZE_RNG] tag_index, + input wire[`LINE_SELECT_BITS-1:0] write_addr, + input wire[`TAG_SELECT_BITS-1:0] tag_index, input wire[`DBANK_LINE_WORDS-1:0][31:0] write_data, input wire fill_sent ); reg [`DBANK_LINE_WORDS-1:0][3:0][7:0] data [`BANK_LINE_COUNT-1:0]; - reg [`TAG_SELECT_SIZE_RNG] tag [`BANK_LINE_COUNT-1:0]; + reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0]; reg valid [`BANK_LINE_COUNT-1:0]; reg dirty [`BANK_LINE_COUNT-1:0];