PERF pipeline stalls and cache

hw/rtl/VX_issue.v

@@ -8,6 +8,10 @@ module VX_issue #(
     input wire      clk,
     input wire      reset,
 
+    `ifdef PERF_ENABLE
+    VX_perf_pipeline_stall_if perf_pipeline_stall_if,
+    `endif
+
     VX_decode_if    decode_if,
     VX_writeback_if writeback_if,   
     
@@ -120,6 +124,21 @@ module VX_issue #(
     `SCOPE_ASSIGN (writeback_rd,      writeback_if.rd);
     `SCOPE_ASSIGN (writeback_data,    writeback_if.data);
 
+    `ifdef PERF_ENABLE
+    reg [63:0] perf_scoreboard_stall;
+    always @ (posedge clk) begin
+        if(reset) begin
+            perf_scoreboard_stall <= 0;
+        end else begin
+            // scoreboard_stall
+            if (ibuf_deq_if.valid & scoreboard_delay) begin 
+                perf_scoreboard_stall <= perf_scoreboard_stall + 64'd1;
+            end
+        end
+    end
+    assign perf_pipeline_stall_if.scoreboard_stall = perf_scoreboard_stall;
+    `endif
+
 `ifdef DBG_PRINT_PIPELINE
     always @(posedge clk) begin
         if (alu_req_if.valid && alu_req_if.ready) begin