define test functions

hw/unit_tests/cache/cachesim.cpp

@@ -58,6 +58,7 @@ void CacheSim::reset() {
 }
 
 void CacheSim::step() {
+  std::cout << timestamp << ": [sim] step()" << std::endl;
   //toggle clock
   cache_->clk = 0;
   this->eval();
@@ -69,6 +70,7 @@ void CacheSim::step() {
   this->eval_reqs();
   this->eval_rsps();
   this->eval_dram_bus();
+  timestamp++;
 }
 
 void CacheSim::eval() {
@@ -80,14 +82,15 @@ void CacheSim::eval() {
 }
 
 void CacheSim::run(){
-#ifndef NDEBUG
+//#ifndef NDEBUG
-  std::cout << timestamp << ": [sim] run()" << std::endl;
+  
-#endif
+//#endif
   this->step();
 
   int valid = 300; 
   
   while (valid > -1) {
+
       this->step();
       if(!cache_->core_req_valid && !cache_->core_rsp_valid){
         valid--; 

hw/unit_tests/cache/testbench.cpp

@@ -5,13 +5,8 @@
 
 #define VCD_OUTPUT 1
 
-int main(int argc, char **argv)
-{
-  //init
-  RAM ram;
-	CacheSim cachesim;
-  cachesim.attach_ram(&ram);
 
+int REQ_RSP(CacheSim *sim){
   unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
   unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
   unsigned int rsp[4] = {0,0,0,0};
@@ -34,21 +29,74 @@ int main(int argc, char **argv)
   read->data = addr; 
   read->tag = 0xff;
   
-	// reset the device
+  // reset the device
-  cachesim.reset();
+  sim->reset();
 
   //queue reqs
-  cachesim.send_req(write);
+  sim->send_req(write);
-  cachesim.send_req(read);
+  sim->send_req(read);
 
-  cachesim.run(); 
+  sim->run();
 
-  bool check = cachesim.assert_equal(data, write->tag);
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+int BACK_PRESSURE(CacheSim *sim){
+  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr; 
+  write->data = data;
+  write->tag = 0xff;
+
+  //read req
+  core_req_t* read = new core_req_t;
+  read->valid = 0xf;
+  read->rw = 0;
+  read->byteen = 0xffff;
+  read->addr = addr;
+  read->data = addr; 
+  read->tag = 0xff;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  for (int i = 0; i < 10; i++){
+    sim->send_req(write);
+  }
+  sim->send_req(read); 
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+int main(int argc, char **argv)
+{
+  //init
+  RAM ram;
+	CacheSim cachesim;
+  cachesim.attach_ram(&ram);
+  int check = REQ_RSP(&cachesim);
   if(check){
     std::cout << "PASSED" << std::endl;
   } else {
     std::cout << "FAILED" << std::endl;
   }
+  
+
 
 	return 0;
 }