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minor update

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This commit is contained in:
Blaise Tine
2021-01-06 19:59:04 -08:00
parent 2b8435471a
commit 146c285aa0
13 changed files with 67 additions and 28 deletions
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2
driver/opae/vlsim/Makefile
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@@ -83,7 +83,7 @@ VL_FLAGS += -DNOPAE
CFLAGS += -DNOPAE CFLAGS += -DNOPAE
# use DPI FPU # use DPI FPU
VL_FLAGS += -DFPU_FAST VL_FLAGS += -DFPU_DPI
PROJECT = libopae-c-vlsim.so PROJECT = libopae-c-vlsim.so

2
driver/rtlsim/Makefile
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@@ -72,7 +72,7 @@ ifdef PERF
endif endif
# use DPI FPU # use DPI FPU
VL_FLAGS += -DFPU_FAST VL_FLAGS += -DFPU_DPI
PROJECT = libvortex.so PROJECT = libvortex.so
# PROJECT = libvortex.dylib # PROJECT = libvortex.dylib

1
hw/opae/vortex_afu.qsf
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@@ -8,7 +8,6 @@ set_global_assignment -name VERILOG_MACRO QUARTUS
set_global_assignment -name VERILOG_MACRO SYNTHESIS set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name VERILOG_MACRO FPU_FAST
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED

14
hw/rtl/VX_fpu_unit.v
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@@ -65,11 +65,11 @@ module VX_fpu_unit #(
assign fpu_to_csr_if.read_wid = fpu_req_if.wid; assign fpu_to_csr_if.read_wid = fpu_req_if.wid;
wire [`FRM_BITS-1:0] fpu_frm = (fpu_req_if.op_mod == `FRM_DYN) ? fpu_to_csr_if.read_frm : fpu_req_if.op_mod; wire [`FRM_BITS-1:0] fpu_frm = (fpu_req_if.op_mod == `FRM_DYN) ? fpu_to_csr_if.read_frm : fpu_req_if.op_mod;
`ifdef FPU_FAST `ifdef FPU_DPI
VX_fp_dpi #( VX_fpu_dpi #(
.TAGW (FPUQ_BITS) .TAGW (FPUQ_BITS)
) fp_core ( ) fpu_dpi (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -97,13 +97,13 @@ module VX_fpu_unit #(
`elsif FPU_FPNEW `elsif FPU_FPNEW
VX_fpnew #( VX_fpu_fpnew #(
.FMULADD (1), .FMULADD (1),
.FDIVSQRT (1), .FDIVSQRT (1),
.FNONCOMP (1), .FNONCOMP (1),
.FCONV (1), .FCONV (1),
.TAGW (FPUQ_BITS) .TAGW (FPUQ_BITS)
) fp_core ( ) fpu_fpnew (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -131,9 +131,9 @@ module VX_fpu_unit #(
`else `else
VX_fp_fpga #( VX_fpu_fpga #(
.TAGW (FPUQ_BITS) .TAGW (FPUQ_BITS)
) fp_core ( ) fpu_fpga (
.clk (clk), .clk (clk),
.reset (fpu_reset), .reset (fpu_reset),

3
hw/rtl/cache/VX_cache.v vendored
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@@ -127,7 +127,8 @@ module VX_cache #(
.WORD_SIZE (WORD_SIZE), .WORD_SIZE (WORD_SIZE),
.NUM_REQS (NUM_REQS), .NUM_REQS (NUM_REQS),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH), .CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.BANK_ADDR_OFFSET(BANK_ADDR_OFFSET) .BANK_ADDR_OFFSET(BANK_ADDR_OFFSET),
.BUFFERED ((NUM_BANKS > 1) && DRAM_ENABLE)
) cache_core_req_bank_sel ( ) cache_core_req_bank_sel (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

35
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
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@@ -11,9 +11,10 @@ module VX_cache_core_req_bank_sel #(
parameter NUM_REQS = 4, parameter NUM_REQS = 4,
// core request tag size // core request tag size
parameter CORE_TAG_WIDTH = 3, parameter CORE_TAG_WIDTH = 3,
// bank offset from beginning of index range // bank offset from beginning of index range
parameter BANK_ADDR_OFFSET = 0 parameter BANK_ADDR_OFFSET = 0,
// buffer the output
parameter BUFFERED = 0
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -46,6 +47,8 @@ module VX_cache_core_req_bank_sel #(
reg [NUM_BANKS-1:0][`WORD_ADDR_WIDTH-1:0] per_bank_core_req_addr_r; reg [NUM_BANKS-1:0][`WORD_ADDR_WIDTH-1:0] per_bank_core_req_addr_r;
reg [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_r; reg [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_r;
reg [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_r; reg [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_r;
reg [NUM_BANKS-1:0] per_bank_core_req_stall;
reg [NUM_REQS-1:0] core_req_ready_r; reg [NUM_REQS-1:0] core_req_ready_r;
reg [NUM_BANKS-1:0] core_req_sel_r; reg [NUM_BANKS-1:0] core_req_sel_r;
wire [NUM_REQS-1:0][`BANK_SELECT_BITS-1:0] core_req_bid; wire [NUM_REQS-1:0][`BANK_SELECT_BITS-1:0] core_req_bid;
@@ -83,7 +86,7 @@ module VX_cache_core_req_bank_sel #(
for (integer j = 0; j < NUM_BANKS; ++j) begin for (integer j = 0; j < NUM_BANKS; ++j) begin
for (integer i = 0; i < NUM_REQS; ++i) begin for (integer i = 0; i < NUM_REQS; ++i) begin
if (core_req_valid[i] && (core_req_bid[i] == `BANK_SELECT_BITS'(j))) begin if (core_req_valid[i] && (core_req_bid[i] == `BANK_SELECT_BITS'(j))) begin
core_req_ready_r[i] = per_bank_core_req_ready[j]; core_req_ready_r[i] = ~per_bank_core_req_stall[j];
core_req_sel_r[i] = 1; core_req_sel_r[i] = 1;
break; break;
end end
@@ -100,15 +103,23 @@ module VX_cache_core_req_bank_sel #(
end end
end end
assign bank_stalls = bank_stalls_r; for (genvar i = 0; i < NUM_BANKS; ++i) begin
assign per_bank_core_req_valid = per_bank_core_req_valid_r; assign per_bank_core_req_stall[i] = ~per_bank_core_req_ready[i] & per_bank_core_req_valid[i];
assign per_bank_core_req_tid = per_bank_core_req_tid_r; VX_pipe_register #(
assign per_bank_core_req_rw = per_bank_core_req_rw_r; .DATAW (1 + `REQS_BITS + 1 + WORD_SIZE + `WORD_ADDR_WIDTH + CORE_TAG_WIDTH + `WORD_WIDTH),
assign per_bank_core_req_byteen = per_bank_core_req_byteen_r; .RESETW (1),
assign per_bank_core_req_addr = per_bank_core_req_addr_r; .DEPTH (BUFFERED)
assign per_bank_core_req_tag = per_bank_core_req_tag_r; ) pipe_reg (
assign per_bank_core_req_data = per_bank_core_req_data_r; .clk (clk),
assign core_req_ready = core_req_ready_r; .reset (reset),
.enable (~per_bank_core_req_stall[i]),
.data_in ({per_bank_core_req_valid_r[i], per_bank_core_req_tid_r[i], per_bank_core_req_rw_r[i], per_bank_core_req_byteen_r[i], per_bank_core_req_addr_r[i], per_bank_core_req_tag_r[i], per_bank_core_req_data_r[i]}),
.data_out ({per_bank_core_req_valid[i], per_bank_core_req_tid[i], per_bank_core_req_rw[i], per_bank_core_req_byteen[i], per_bank_core_req_addr[i], per_bank_core_req_tag[i], per_bank_core_req_data[i]})
);
end
assign core_req_ready = core_req_ready_r;
assign bank_stalls = bank_stalls_r;
end else begin end else begin

2
hw/rtl/fp_cores/VX_fp_dpi.v → hw/rtl/fp_cores/VX_fpu_dpi.v
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@@ -3,7 +3,7 @@
`include "VX_define.vh" `include "VX_define.vh"
`include "float_dpi.vh" `include "float_dpi.vh"
module VX_fp_dpi #( module VX_fpu_dpi #(
parameter TAGW = 1 parameter TAGW = 1
) ( ) (
input wire clk, input wire clk,

2
hw/rtl/fp_cores/VX_fp_fpga.v → hw/rtl/fp_cores/VX_fpu_fpga.v
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@@ -1,6 +1,6 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_fp_fpga #( module VX_fpu_fpga #(
parameter TAGW = 1 parameter TAGW = 1
) ( ) (
input wire clk, input wire clk,

2
hw/rtl/fp_cores/VX_fpnew.v → hw/rtl/fp_cores/VX_fpu_fpnew.v
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@@ -3,7 +3,7 @@
`include "defs_div_sqrt_mvp.sv" `include "defs_div_sqrt_mvp.sv"
`TRACING_OFF `TRACING_OFF
module VX_fpnew module VX_fpu_fpnew
#( #(
parameter TAGW = 1, parameter TAGW = 1,
parameter FMULADD = 1, parameter FMULADD = 1,

27
hw/rtl/libs/VX_reset_relay.v Normal file
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@@ -0,0 +1,27 @@
`include "VX_platform.vh"
module VX_reset_relay #(
parameter NUM_NODES = 1,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
output wire [NUM_NODES-1:0] reset_out
);
if (PASSTHRU == 0) begin
reg [NUM_NODES-1:0] reset_r;
always @(posedge clk) begin
for (integer i = 0; i < NUM_NODES; ++i) begin
reset_r[i] <= reset;
end
end
assign reset_out = reset_r;
end else begin
`UNUSED_VAR (clk)
for (genvar i = 0; i < NUM_NODES; ++i) begin
assign reset_out[i] = reset;
end
end
endmodule

3
hw/simulate/Makefile
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@@ -47,6 +47,9 @@ VL_FLAGS += verilator.vlt
VL_FLAGS += --exe $(SRCS) $(RTL_INCLUDE) VL_FLAGS += --exe $(SRCS) $(RTL_INCLUDE)
VL_FLAGS += --cc Vortex.v --top-module $(TOP) VL_FLAGS += --cc Vortex.v --top-module $(TOP)
// Use FPNEW PFU core
VL_FLAGS += -DFPU_FPNEW
DBG_FLAGS += -DVCD_OUTPUT $(DBG_FLAGS) DBG_FLAGS += -DVCD_OUTPUT $(DBG_FLAGS)
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')

1
hw/simulate/simulator.cpp
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@@ -86,7 +86,6 @@ void Simulator::reset() {
vortex_->reset = 0; vortex_->reset = 0;
// Turn on assertion after reset // Turn on assertion after reset
printf("*** enabling assertion at tick: %ld", timestamp);
Verilated::assertOn(true); Verilated::assertOn(true);
} }

1
hw/syn/quartus/project.tcl
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@@ -39,7 +39,6 @@ set_global_assignment -name VERILOG_MACRO QUARTUS
set_global_assignment -name VERILOG_MACRO SYNTHESIS set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name VERILOG_MACRO FPU_FAST
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED