diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v
index f2329ef1..8613eceb 100644
--- a/hw/rtl/VX_icache_stage.v
+++ b/hw/rtl/VX_icache_stage.v
@@ -14,7 +14,7 @@ module VX_icache_stage (
     VX_cache_core_req_if    icache_req_if
 );
 
-    reg[`NUM_THREADS-1:0] threads_active[`NUM_WARPS-1:0];
+    reg[`NUM_THREADS-1:0] pending_threads[`NUM_WARPS-1:0];
 
     wire valid_inst = (| fe_inst_meta_fi.valid);
 
@@ -34,7 +34,7 @@ module VX_icache_stage (
     assign {fe_inst_meta_id.inst_pc, rsp_wb, rsp_rd, fe_inst_meta_id.warp_num} = icache_rsp_if.core_rsp_tag;
 
     assign fe_inst_meta_id.instruction = icache_rsp_if.core_rsp_data[0][31:0];
-    assign fe_inst_meta_id.valid       = icache_rsp_if.core_rsp_valid ? threads_active[fe_inst_meta_id.warp_num] : 0;
+    assign fe_inst_meta_id.valid       = icache_rsp_if.core_rsp_valid ? pending_threads[fe_inst_meta_id.warp_num] : 0;
 
     assign icache_stage_wid            = fe_inst_meta_id.warp_num;
     assign icache_stage_valids         = fe_inst_meta_id.valid & {`NUM_THREADS{!icache_stage_delay}};
@@ -50,11 +50,11 @@ module VX_icache_stage (
     always @(posedge clk) begin
         if (reset) begin
             for (i = 0; i < `NUM_WARPS; i = i + 1) begin
-                threads_active[i] <= 0;
+                pending_threads[i] <= 0;
             end
         end else begin
-            if (valid_inst && !icache_stage_delay) begin
-                threads_active[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid;                
+            if (icache_req_if.core_req_valid && icache_req_if.core_req_ready) begin
+                pending_threads[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid;                
             end
         end
     end
diff --git a/hw/rtl/VX_scheduler.v b/hw/rtl/VX_scheduler.v
index d58fdce8..bbff0c83 100644
--- a/hw/rtl/VX_scheduler.v
+++ b/hw/rtl/VX_scheduler.v
@@ -67,7 +67,7 @@ module VX_scheduler (
         
             if (valid_wb 
              && (0 == (rename_table[writeback_if.warp_num][writeback_if.rd] & ~writeback_if.valid))) begin
-                   count_valid <= count_valid - 1;
+                count_valid <= count_valid - 1;
             end
 
             if (!schedule_delay && wb_inc) begin
diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v
index ac444caa..d26f75f2 100644
--- a/hw/rtl/cache/VX_cache_miss_resrv.v
+++ b/hw/rtl/cache/VX_cache_miss_resrv.v
@@ -113,7 +113,6 @@ module VX_cache_miss_resrv #(
         if (reset) begin
             valid_table <= 0;
             ready_table <= 0;
-            addr_table  <= 0;
             size        <= 0;
             head_ptr    <= 0;
             tail_ptr    <= 0;
diff --git a/hw/rtl/libs/VX_generic_stack.v b/hw/rtl/libs/VX_generic_stack.v
index e2ce3584..fdebbacf 100644
--- a/hw/rtl/libs/VX_generic_stack.v
+++ b/hw/rtl/libs/VX_generic_stack.v
@@ -15,11 +15,9 @@ module VX_generic_stack #(
     reg [DEPTH - 1:0] ptr;
     reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
 
-    integer i;
     always @(posedge clk) begin
         if (reset) begin
             ptr <= 0;
-            for (i = 0; i < (1 << DEPTH); i=i+1) stack[i] <= 0;
         end else if (push) begin
             stack[ptr]   <= q1;
             stack[ptr+1] <= q2;