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register file refactoring

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This commit is contained in:
Blaise Tine
2020-12-05 01:40:50 -08:00
parent 478d971389
commit 13a5370254
33 changed files with 524 additions and 605 deletions
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20
hw/rtl/libs/VX_generic_register.v
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@@ -5,25 +5,25 @@ module VX_generic_register #(
parameter R = N,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
input wire stall,
input wire flush,
input wire[N-1:0] in,
output wire[N-1:0] out
input wire clk,
input wire reset,
input wire stall,
input wire flush,
input wire[N-1:0] data_in,
output wire[N-1:0] data_out
);
if (PASSTHRU) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (stall)
assign out = flush ? N'(0) : in;
assign data_out = flush ? N'(0) : data_in;
end else begin
reg [N-1:0] value;
if (R != 0) begin
always @(posedge clk) begin
if (~stall) begin
value <= in;
value <= data_in;
end
if (reset || flush) begin
value[N-1:N-R] <= R'(0);
@@ -34,12 +34,12 @@ module VX_generic_register #(
`UNUSED_VAR (flush)
always @(posedge clk) begin
if (~stall) begin
value <= in;
value <= data_in;
end
end
end
assign out = value;
assign data_out = value;
end
endmodule