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register file refactoring

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This commit is contained in:
Blaise Tine
2020-12-05 01:40:50 -08:00
parent 478d971389
commit 13a5370254
33 changed files with 524 additions and 605 deletions
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98
hw/rtl/libs/VX_dp_ram.v
View File

@@ -5,7 +5,7 @@ module VX_dp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter BUFFERED = 1,
parameter BUFFERED = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
@@ -26,8 +26,10 @@ module VX_dp_ram #(
localparam DATA32W = DATAW / 32;
localparam BYTEEN32W = BYTEENW / 4;
if (FASTRAM) begin
if (BUFFERED) begin
//`ifndef QUARTUS
if (FASTRAM) begin
if (BUFFERED) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
@@ -207,5 +209,95 @@ module VX_dp_ram #(
end
end
/*`else
localparam OUTDATA_REG_B = BUFFERED ? "CLOCK0" : "UNREGISTERED";
localparam RAM_BLOCK_TYPE = FASTRAM ? "MLAB" : "AUTO";
if (RWCHECK) begin
altsyncram #(
.init_file (),
.operation_mode ("DUAL_PORT"),
.numwords_a (SIZE),
.numwords_b (SIZE),
.widthad_a (ADDRW),
.widthad_b (ADDRW),
.width_a (DATAW),
.width_b (DATAW),
.width_byteena_a(BYTEENW),
.address_reg_b ("CLOCK0"),
.outdata_reg_b (OUTDATA_REG_B),
.ram_block_type (RAM_BLOCK_TYPE)
) mem (
.clocken0 (1'b1),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.clock0 (clk),
.clock1 (),
.address_a (waddr),
.address_b (raddr),
.byteena_a (byteen),
.byteena_b (1'b1),
.wren_a (wren),
.wren_b (1'b0),
.data_a (din),
.data_b (),
.rden_a (),
.rden_b (1'b1),
.q_a (),
.q_b (dout),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.eccstatus ()
);
end else begin
`NO_RW_RAM_CHECK altsyncram #(
.init_file (),
.operation_mode ("DUAL_PORT"),
.numwords_a (SIZE),
.numwords_b (SIZE),
.widthad_a (ADDRW),
.widthad_b (ADDRW),
.width_a (DATAW),
.width_b (DATAW),
.width_byteena_a(BYTEENW),
.outdata_reg_b (OUTDATA_REG_B),
.ram_block_type (RAM_BLOCK_TYPE)
) mem (
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.clock0 (clk),
.clock1 (clk),
.address_a (waddr),
.address_b (raddr),
.byteena_a (byteen),
.byteena_b (1'b1),
.wren_a (wren),
.wren_b (1'b0),
.data_a (din),
.data_b (),
.rden_a (),
.rden_b (1'b1),
.q_a (),
.q_b (dout),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.eccstatus ()
);
end
`endif*/
endmodule
`TRACING_ON

20
hw/rtl/libs/VX_generic_register.v
View File

@@ -5,25 +5,25 @@ module VX_generic_register #(
parameter R = N,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
input wire stall,
input wire flush,
input wire[N-1:0] in,
output wire[N-1:0] out
input wire clk,
input wire reset,
input wire stall,
input wire flush,
input wire[N-1:0] data_in,
output wire[N-1:0] data_out
);
if (PASSTHRU) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (stall)
assign out = flush ? N'(0) : in;
assign data_out = flush ? N'(0) : data_in;
end else begin
reg [N-1:0] value;
if (R != 0) begin
always @(posedge clk) begin
if (~stall) begin
value <= in;
value <= data_in;
end
if (reset || flush) begin
value[N-1:N-R] <= R'(0);
@@ -34,12 +34,12 @@ module VX_generic_register #(
`UNUSED_VAR (flush)
always @(posedge clk) begin
if (~stall) begin
value <= in;
value <= data_in;
end
end
end
assign out = value;
assign data_out = value;
end
endmodule

12
hw/rtl/libs/VX_stream_arbiter.v
View File

@@ -106,12 +106,12 @@ module VX_stream_arbiter #(
.N(1 + DATAW),
.R(1)
) pipe_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.in ({sel_valid, data_in[sel_idx]}),
.out ({valid_out, data_out})
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.data_in ({sel_valid, data_in[sel_idx]}),
.data_out ({valid_out, data_out})
);
for (genvar i = 0; i < NUM_REQS; i++) begin