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refactoring fixes

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This commit is contained in:
Blaise Tine
2020-04-14 19:39:59 -04:00
parent 22c8da7490
commit 12dc4d6874
624 changed files with 600 additions and 28528 deletions
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hw/syn/synopsys/Vortex.ddc
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4
hw/syn/synopsys/esyn.tcl
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@@ -1,5 +1,5 @@
#set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db]
set search_path [concat ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db]
#set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache ../../models/memory/cln28hpm/2d_hardmacro_db]
set search_path [concat ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache ../../models/memory/cln28hpm/2d_hardmacro_db]
set link_library [concat ./NanGate_15nm_OCL.db]
set symbol_library {}
set target_library [concat ./NanGate_15nm_OCL.db]

2
hw/syn/synopsys/fsyn.tcl
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@@ -1,4 +1,4 @@
set search_path [concat ../models/memory/cln28hpm/rf2_128x128_wm1 ../models/memory/cln28hpm/rf2_256x128_wm1 ../models/memory/cln28hpm/rf2_256_19_wm0 ../models/memory/cln28hpm/rf2_32x128_wm1 ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache]
set search_path [concat ../../models/memory/cln28hpm/rf2_128x128_wm1 ../../models/memory/cln28hpm/rf2_256x128_wm1 ../../models/memory/cln28hpm/rf2_256_19_wm0 ../../models/memory/cln28hpm/rf2_32x128_wm1 ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache]
set link_library [concat NanGate_15nm_OCL.db]
set symbol_library {}
set target_library [concat NanGate_15nm_OCL.db]

2
hw/syn/synopsys/syn.tcl
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@@ -1,4 +1,4 @@
set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db]
set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache ../../models/memory/cln28hpm/2d_hardmacro_db]
set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb]
set symbol_library {}
set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db]