wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Modelsim basic sim

Browse Source
This commit is contained in:
felsabbagh3
2019-10-26 00:34:57 -04:00
parent 9110e8367e
commit 1181af1df2
25 changed files with 72 additions and 501 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
rtl/cache/VX_cache_bank_valid.v vendored
View File

@@ -10,13 +10,15 @@ module VX_cache_bank_valid
output reg [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks
);
genvar t_id;
always @(*) begin
thread_track_banks = 0;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin
thread_track_banks[i_p_addr[t_id][4:2]][t_id] = i_p_valid[t_id];
end
end
generate
integer t_id;
always @(*) begin
thread_track_banks = 0;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin
thread_track_banks[i_p_addr[t_id][4:2]][t_id] = i_p_valid[t_id];
end
end
endgenerate
endmodule