Modelsim basic sim
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@@ -16,13 +16,14 @@ module VX_writeback (
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);
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assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
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wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid);
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wire mem_wb = (VX_mem_wb.wb != 0) && (|VX_mem_wb.wb_valid);
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wire csr_wb = (VX_csr_wb.wb != 0) && (|VX_csr_wb.valid);
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assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
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assign VX_writeback_inter.write_data = exec_wb ? VX_inst_exec_wb.alu_result :
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csr_wb ? VX_csr_wb.csr_result :
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mem_wb ? VX_mem_wb.loaded_data :
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