verilator suppor for opae (partial)

driver/common/vx_utils.cpp

@@ -2,7 +2,7 @@
 #include <fstream>
 #include <cstring>
 #include <vortex.h>
-#include <config.h>
+#include <VX_config.h>
 
 extern int vx_dev_caps(int caps_id) {
   switch (caps_id) {

driver/opae/Makefile

@@ -1,7 +1,7 @@
 
 CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors
 
-CXXFLAGS += -I../include -I/tools/opae/1.4.0/include  -I../../runtime
+CXXFLAGS += -I../include -I/tools/opae/1.4.0/include  -I../../hw
 
 LDFLAGS += -L/tools/opae/1.4.0/lib
 

driver/rtlsim/Makefile

@@ -19,6 +19,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
 
 #DEBUG = 1
+AFU=1
 
 CFLAGS += -fPIC
 
@@ -27,6 +28,8 @@ CFLAGS += -DUSE_RTLSIM $(MULTICORE)
 LDFLAGS += -shared -pthread
 # LDFLAGS += -dynamiclib -pthread
 
+TOP = Vortex_Socket
+
 SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
 
 RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache
@@ -48,14 +51,22 @@ else
 	VL_FLAGS += -DNDEBUG
 endif
 
+# AFU
+ifdef AFU
+    TOP = vortex_afu_sim
+	VL_FLAGS += -DNOPAE
+	CFLAGS += -DNOPAE
+	RTL_INCLUDE += -I../../hw/opae  -I../../hw/opae/ccip
+endif
+
 PROJECT = libvortex.so
 # PROJECT = libvortex.dylib
 
 all: $(PROJECT)
 	
 $(PROJECT): $(SRCS)
-	verilator --exe --cc Vortex_Socket.v $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
-	make -j -C obj_dir -f VVortex_Socket.mk
+	verilator --exe --cc $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
+	make -j -C obj_dir -f V$(TOP).mk
 
 clean:
 	rm -rf $(PROJECT) obj_dir

driver/rtlsim/ram.h

@@ -0,0 +1,64 @@
+#pragma once
+
+#include <stdio.h>
+#include <stdint.h>
+
+class RAM {
+private:
+
+  mutable uint8_t *mem_[(1 << 12)];      
+
+  uint8_t *get(uint32_t address) const {
+    uint32_t block_addr   = address >> 20;
+    uint32_t block_offset = address & 0x000FFFFF;
+    if (mem_[block_addr] == NULL) {
+      mem_[block_addr] = new uint8_t[(1 << 20)];
+    }
+    return mem_[block_addr] + block_offset;
+  }
+
+public:
+
+  RAM() {
+    for (uint32_t i = 0; i < (1 << 12); i++) {
+      mem_[i] = NULL;
+    }
+  }
+
+  ~RAM() {
+    this->clear();
+  }
+
+  size_t size() const {
+    return (1ull << 32);
+  }
+
+  void clear() {
+    for (uint32_t i = 0; i < (1 << 12); i++) {
+      if (mem_[i]) {
+        delete mem_[i];
+        mem_[i] = NULL;
+      }
+    }
+  }
+
+  void read(uint32_t address, uint32_t length, uint8_t *data) const {
+    for (unsigned i = 0; i < length; i++) {
+      data[i] = *this->get(address + i);
+    }
+  }
+
+  void write(uint32_t address, uint32_t length, const uint8_t *data) {
+    for (unsigned i = 0; i < length; i++) {
+      *this->get(address + i) = data[i];
+    }
+  }
+
+  uint8_t& operator[](uint32_t address) {
+    return *get(address);
+  }
+
+  const uint8_t& operator[](uint32_t address) const {
+    return *get(address);
+  }
+};

driver/rtlsim/simulator.cpp

@@ -0,0 +1,70 @@
+#include "simulator.h"
+#include <iostream>
+#include <fstream>
+#include <iomanip>
+
+uint64_t timestamp = 0;
+
+double sc_time_stamp() { 
+  return timestamp;
+}
+
+Simulator::Simulator() {    
+  // force random values for unitialized signals
+  const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+50"};
+  Verilated::commandArgs(3, args);
+
+  vortex_ = new Vvortex_afu_sim();
+
+#ifdef VCD_OUTPUT
+  Verilated::traceEverOn(true);
+  trace_ = new VerilatedVcdC;
+  vortex_->trace(trace_, 99);
+  trace_->open("trace.vcd");
+#endif  
+}
+
+Simulator::~Simulator() {
+#ifdef VCD_OUTPUT
+  trace_->close();
+#endif
+  delete vortex_;
+}
+
+void Simulator::reset() {     
+#ifndef NDEBUG
+  std::cout << timestamp << ": [sim] reset()" << std::endl;
+#endif 
+  vortex_->reset = 1;
+  this->step();  
+  vortex_->reset = 0;
+
+  dram_rsp_vec_.clear();
+}
+
+void Simulator::step() {
+  vortex_->clk = 0;
+  this->eval();
+
+  vortex_->clk = 1;
+  this->eval();
+
+  avs_driver();
+  ccip_driver();
+}
+
+void Simulator::eval() {
+  vortex_->eval();
+#ifdef VCD_OUTPUT
+  trace_->dump(timestamp);
+#endif
+  ++timestamp;
+}
+
+void Simulator::avs_driver() {
+  //--
+}
+
+ void Simulator::ccip_driver() {
+   //--
+ }

driver/rtlsim/simulator.h

@@ -0,0 +1,59 @@
+#pragma once
+
+#include "Vvortex_afu_sim.h"
+#include "Vvortex_afu_sim__Syms.h"
+#include "verilated.h"
+
+#ifdef VCD_OUTPUT
+#include <verilated_vcd_c.h>
+#endif
+
+#include <VX_config.h>
+#include "ram.h"
+
+#include <ostream>
+#include <vector>
+
+#define ENABLE_DRAM_STALLS
+#define DRAM_LATENCY 100
+#define DRAM_RQ_SIZE 16
+#define DRAM_STALLS_MODULO 16
+
+typedef struct {
+  int cycles_left;  
+  uint8_t *data;
+  unsigned tag;
+} dram_req_t;
+
+class Simulator {
+public:
+  
+  Simulator();
+  virtual ~Simulator();
+
+  void reset();
+  
+  void step();  
+
+  int mmio_read(uint64_t addr, uint64_t* value);
+
+  int mmio_write(uint64_t addr, uint64_t value);
+  
+private:  
+
+  void eval(); 
+
+  void avs_driver();
+
+  void ccip_driver(); 
+  
+  std::vector<dram_req_t> dram_rsp_vec_;
+
+  RAM ram_;
+  Vvortex_afu_sim *vortex_;
+  
+
+#ifdef VCD_OUTPUT
+  VerilatedVcdC *trace_;
+#endif
+};

driver/rtlsim/vortex.cpp

@@ -7,7 +7,6 @@
 #include <chrono>
 
 #include <vortex.h>
-#include <ram.h>
 #include <simulator.h>
 
 ///////////////////////////////////////////////////////////////////////////////
@@ -60,7 +59,6 @@ class vx_device {
 public:
     vx_device() {        
         mem_allocation_ = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR);
-        simulator_.attach_ram(&ram_);
     } 
 
     ~vx_device() {     
@@ -146,7 +144,6 @@ public:
 private:
 
     size_t mem_allocation_;     
-    RAM ram_;
     Simulator simulator_;
     std::future<void> future_;
 };

driver/simx/Makefile

@@ -1,7 +1,7 @@
 CFLAGS += -std=c++11 -O3 -Wall -Wextra -pedantic -Wfatal-errors
 #CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -pedantic -Wfatal-errors
 
-CFLAGS += -I../../include -I../../../simX/include -I../../../runtime
+CFLAGS += -I../../include -I../../../simX/include -I../../../hw
 
 CFLAGS += -fPIC
 

driver/simx/vortex.cpp

@@ -9,7 +9,7 @@
 
 #include <vortex.h>
 #include <core.h>
-#include <config.h>
+#include <VX_config.h>
 
 #define PAGE_SIZE 4096
 

driver/tests/basic/Makefile

@@ -15,6 +15,7 @@ VX_API = $(VX_RT_PATH)/vx_api/vx_api.c
 VX_FIO = $(VX_RT_PATH)/fileio/fileio.S
 
 VX_CFLAGS = -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,$(VX_RT_PATH)/startup/vx_link.ld -ffreestanding -nostartfiles -Wl,--gc-sections
+VX_CFLAGS += -I../../../hw 
 
 VX_SRCS = kernel.c
 

driver/tests/basic/common.h

@@ -1,8 +1,8 @@
 #ifndef _COMMON_H_
 #define _COMMON_H_
 
-#define DEV_MEM_SRC_ADDR 0x10000000
-#define DEV_MEM_DST_ADDR 0x20000000
+#define DEV_MEM_SRC_ADDR 0x10000040
+#define DEV_MEM_DST_ADDR 0x20000080
 #define NUM_BLOCKS       64
 
 #endif

driver/tests/basic/kernel.c

@@ -1,5 +1,5 @@
 #include <stdint.h>
-#include "config.h"
+#include <VX_config.h>
 #include "intrinsics/vx_intrinsics.h"
 #include "common.h"
 

driver/tests/demo/Makefile

@@ -14,6 +14,7 @@ VX_API = $(VX_RT_PATH)/vx_api/vx_api.c
 #VX_FIO = $(VX_RT_PATH)/fileio/fileio.S
 
 VX_CFLAGS = -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,$(VX_RT_PATH)/startup/vx_link.ld -ffreestanding -nostartfiles -Wl,--gc-sections
+VX_CFLAGS += -I../../../hw 
 
 VX_SRCS = kernel.c