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refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2

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Blaise Tine
2020-11-08 01:31:46 -08:00
parent b14007f930
commit 10505caae1
19 changed files with 602 additions and 534 deletions
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12
hw/rtl/cache/VX_cache.v vendored
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@@ -46,7 +46,7 @@ module VX_cache #(
parameter CORE_TAG_WIDTH = 4,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 4,
parameter CORE_TAG_ID_BITS = 0,
// dram request tag size
parameter DRAM_TAG_WIDTH = 28,
@@ -407,15 +407,15 @@ module VX_cache #(
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
) cache_core_rsp_merge (
.clk (clk),
.reset (reset),
.per_bank_core_rsp_tid (per_bank_core_rsp_tid),
.reset (reset),
.per_bank_core_rsp_valid (per_bank_core_rsp_valid),
.per_bank_core_rsp_data (per_bank_core_rsp_data),
.per_bank_core_rsp_tag (per_bank_core_rsp_tag),
.per_bank_core_rsp_tid (per_bank_core_rsp_tid),
.per_bank_core_rsp_data (per_bank_core_rsp_data),
.per_bank_core_rsp_ready (per_bank_core_rsp_ready),
.core_rsp_valid (core_rsp_valid),
.core_rsp_data (core_rsp_data),
.core_rsp_valid (core_rsp_valid),
.core_rsp_tag (core_rsp_tag),
.core_rsp_data (core_rsp_data),
.core_rsp_ready (core_rsp_ready)
);