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refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2

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This commit is contained in:
Blaise Tine
2020-11-08 01:31:46 -08:00
parent b14007f930
commit 10505caae1
19 changed files with 602 additions and 534 deletions
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94
hw/rtl/VX_csr_io_arb.v
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@@ -33,52 +33,66 @@ module VX_csr_io_arb #(
output wire [31:0] csr_io_rsp_data_out,
input wire csr_io_rsp_ready_out
);
if (NUM_REQUESTS == 1) begin
if (NUM_REQUESTS > 1) begin
for (genvar i = 0; i < NUM_REQUESTS; i++) begin
assign csr_io_req_valid_out[i] = csr_io_req_valid_in && (request_id == `REQS_BITS'(i));
assign csr_io_req_addr_out[i] = csr_io_req_addr_in;
assign csr_io_req_rw_out[i] = csr_io_req_rw_in;
assign csr_io_req_data_out[i] = csr_io_req_data_in;
end
assign csr_io_req_ready_in = csr_io_req_ready_out[request_id];
///////////////////////////////////////////////////////////////////////
wire [REQS_BITS-1:0] rsp_idx;
wire [NUM_REQUESTS-1:0] rsp_1hot;
VX_fixed_arbiter #(
.N(NUM_REQUESTS)
) rsp_arb (
.clk (clk),
.reset (reset),
.requests (csr_io_rsp_valid_in),
`UNUSED_PIN (grant_valid),
.grant_index (rsp_idx),
.grant_onehot (rsp_1hot)
);
wire stall = csr_io_rsp_valid_out && ~csr_io_rsp_ready_out;
VX_generic_register #(
.N(1 + 32),
.PASSTHRU(NUM_REQUESTS <= 2)
) pipe_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.in ({csr_io_rsp_valid_in[rsp_idx], csr_io_rsp_data_in[rsp_idx]}),
.out ({csr_io_rsp_valid_out, csr_io_rsp_data_out})
);
for (genvar i = 0; i < NUM_REQUESTS; i++) begin
assign csr_io_rsp_ready_in[i] = rsp_1hot[i] && ~stall;
end
end else begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (request_id)
assign csr_io_req_valid_out = csr_io_req_valid_in;
assign csr_io_req_rw_out = csr_io_req_rw_in;
assign csr_io_req_addr_out = csr_io_req_addr_in;
assign csr_io_req_data_out = csr_io_req_data_in;
assign csr_io_req_ready_in = csr_io_req_ready_out;
assign csr_io_req_valid_out = csr_io_req_valid_in;
assign csr_io_req_addr_out = csr_io_req_addr_in;
assign csr_io_req_rw_out = csr_io_req_rw_in;
assign csr_io_req_data_out = csr_io_req_data_in;
assign csr_io_req_ready_in = csr_io_req_ready_out;
assign csr_io_rsp_valid_out = csr_io_rsp_valid_in;
assign csr_io_rsp_data_out = csr_io_rsp_data_in;
assign csr_io_rsp_ready_in = csr_io_rsp_ready_out;
end else begin
for (genvar i = 0; i < NUM_REQUESTS; i++) begin
assign csr_io_req_valid_out[i] = csr_io_req_valid_in && (request_id == `REQS_BITS'(i));
assign csr_io_req_rw_out[i] = csr_io_req_rw_in;
assign csr_io_req_addr_out[i] = csr_io_req_addr_in;
assign csr_io_req_data_out[i] = csr_io_req_data_in;
end
assign csr_io_req_ready_in = csr_io_req_ready_out[request_id];
reg [REQS_BITS-1:0] bus_rsp_sel;
VX_fixed_arbiter #(
.N(NUM_REQUESTS)
) arbiter (
.clk (clk),
.reset (reset),
.requests (csr_io_rsp_valid_in),
.grant_index (bus_rsp_sel),
`UNUSED_PIN (grant_valid),
`UNUSED_PIN (grant_onehot)
);
assign csr_io_rsp_valid_out = csr_io_rsp_valid_in [bus_rsp_sel];
assign csr_io_rsp_data_out = csr_io_rsp_data_in [bus_rsp_sel];
for (genvar i = 0; i < NUM_REQUESTS; i++) begin
assign csr_io_rsp_ready_in[i] = csr_io_rsp_ready_out && (bus_rsp_sel == `REQS_BITS'(i));
end
assign csr_io_rsp_valid_out = csr_io_rsp_valid_in;
assign csr_io_rsp_data_out = csr_io_rsp_data_in;
assign csr_io_rsp_ready_in = csr_io_rsp_ready_out;
end