adding support for verilator-driven AFU driver: vlsim
This commit is contained in:
Blaise Tine
261
driver/opae/vlsim/opae_sim.cpp
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261
driver/opae/vlsim/opae_sim.cpp
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#include "opae_sim.h"
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#include <iostream>
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#include <fstream>
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#include <iomanip>
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#define CCI_LATENCY 8
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#define CCI_RQ_SIZE 16
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#define CCI_WQ_SIZE 16
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#define ENABLE_DRAM_STALLS
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#define DRAM_LATENCY 4
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#define DRAM_RQ_SIZE 16
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#define DRAM_STALLS_MODULO 16
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uint64_t timestamp = 0;
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double sc_time_stamp() {
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return timestamp;
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}
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opae_sim::opae_sim() {
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// force random values for unitialized signals
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Verilated::randReset(2);
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Verilated::randSeed(50);
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// Turn off assertion before reset
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Verilated::assertOn(false);
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stop_ = false;
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vortex_afu_ = new Vvortex_afu_shim();
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#ifdef VCD_OUTPUT
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Verilated::traceEverOn(true);
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trace_ = new VerilatedVcdC();
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vortex_afu_->trace(trace_, 99);
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trace_->open("trace.vcd");
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#endif
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future_ = std::async(std::launch::async, [&]{
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this->reset();
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while (stop_) {
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this->step();
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}
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});
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}
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opae_sim::~opae_sim() {
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stop_ = true;
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if (future_.valid()) {
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future_.wait();
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}
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#ifdef VCD_OUTPUT
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trace_->close();
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#endif
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delete vortex_afu_;
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}
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void opae_sim::prepare_buffer(uint64_t len, void **buf_addr, uint64_t *wsid, int flags) {
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host_alloc_t alloc;
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alloc.data = new uint8_t[len];
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alloc.size = len;
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*wsid = host_allocs_.size();
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host_allocs_.push_back(alloc);
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}
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void opae_sim::release_buffer(uint64_t wsid) {
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delete [] host_allocs_[wsid].data;
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host_allocs_.erase(host_allocs_.begin() + wsid);
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}
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void opae_sim::get_io_address(uint64_t wsid, uint64_t *ioaddr) {
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*ioaddr = (intptr_t)host_allocs_[wsid].data / GLOBAL_BLOCK_SIZE;
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}
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void opae_sim::write_mmio64(uint32_t mmio_num, uint64_t offset, uint64_t value) {
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vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid = 1;
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vortex_afu_->vcp2af_sRxPort_c0_hdr_resp_type = offset;
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memcpy(vortex_afu_->vcp2af_sRxPort_c0_data, &value, 8);
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}
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void opae_sim::read_mmio64(uint32_t mmio_num, uint64_t offset, uint64_t *value) {
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vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid = 1;
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vortex_afu_->vcp2af_sRxPort_c0_hdr_resp_type = offset;
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while (0 == vortex_afu_->af2cp_sTxPort_c2_mmioRdValid);
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*value = vortex_afu_->af2cp_sTxPort_c2_data;
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}
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///////////////////////////////////////////////////////////////////////////////
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void opae_sim::reset() {
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vortex_afu_->clk = 0;
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this->eval();
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vortex_afu_->clk = 1;
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this->eval();
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}
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void opae_sim::step() {
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vortex_afu_->clk = 0;
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this->eval();
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vortex_afu_->clk = 1;
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this->eval();
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this->sRxPort_bus();
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this->sTxPort_bus();
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this->avs_bus();
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}
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void opae_sim::eval() {
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vortex_afu_->eval();
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#ifdef VCD_OUTPUT
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trace_->dump(timestamp);
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#endif
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++timestamp;
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}
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void opae_sim::sRxPort_bus() {
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// schedule CCI read responses
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int cci_rd_index = -1;
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for (int i = 0; i < cci_reads_.size(); i++) {
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if (cci_reads_[i].cycles_left > 0) {
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cci_reads_[i].cycles_left -= 1;
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}
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if ((cci_rd_index == -1)
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&& (cci_reads_[i].cycles_left == 0)) {
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cci_rd_index = i;
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}
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}
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// schedule CCI write responses
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int cci_wr_index = -1;
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for (int i = 0; i < cci_writes_.size(); i++) {
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if (cci_writes_[i].cycles_left > 0) {
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cci_writes_[i].cycles_left -= 1;
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}
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if ((cci_wr_index == -1)
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&& (cci_writes_[i].cycles_left == 0)) {
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cci_wr_index = i;
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}
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}
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// send CCI read response
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vortex_afu_->vcp2af_sRxPort_c0_rspValid = 0;
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if (cci_rd_index != -1) {
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vortex_afu_->vcp2af_sRxPort_c0_rspValid = 1;
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memcpy(vortex_afu_->vcp2af_sRxPort_c0_data, cci_reads_[cci_rd_index].block.data(), GLOBAL_BLOCK_SIZE);
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vortex_afu_->vcp2af_sRxPort_c0_hdr_mdata = cci_reads_[cci_rd_index].mdata;
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cci_reads_.erase(cci_reads_.begin() + cci_rd_index);
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}
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// send CCI write response
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vortex_afu_->vcp2af_sRxPort_c1_rspValid = 0;
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if (cci_wr_index != -1) {
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vortex_afu_->vcp2af_sRxPort_c1_rspValid = 1;
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vortex_afu_->vcp2af_sRxPort_c1_hdr_mdata = cci_writes_[cci_wr_index].mdata;
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cci_writes_.erase(cci_writes_.begin() + cci_wr_index);
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}
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// mmio
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vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid = 0;
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vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid = 0;
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}
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void opae_sim::sTxPort_bus() {
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// check read queue size
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vortex_afu_->vcp2af_sRxPort_c0_TxAlmFull = (cci_reads_.size() >= CCI_RQ_SIZE);
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// check write queue size
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vortex_afu_->vcp2af_sRxPort_c1_TxAlmFull = (cci_writes_.size() >= CCI_WQ_SIZE);
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// process read requests
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if (vortex_afu_->af2cp_sTxPort_c0_valid && !vortex_afu_->vcp2af_sRxPort_c0_TxAlmFull) {
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cci_rd_req_t cci_req;
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cci_req.cycles_left = CCI_LATENCY;
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cci_req.mdata = vortex_afu_->af2cp_sTxPort_c0_hdr_mdata;
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auto host_ptr = this->find_host_ptr(vortex_afu_->af2cp_sTxPort_c0_hdr_address);
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memcpy(cci_req.block.data(), host_ptr, GLOBAL_BLOCK_SIZE);
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cci_reads_.push_back(cci_req);
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}
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// process write requests
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if (vortex_afu_->af2cp_sTxPort_c1_valid && !vortex_afu_->vcp2af_sRxPort_c1_TxAlmFull) {
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cci_wr_req_t cci_req;
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cci_req.cycles_left = CCI_LATENCY;
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cci_req.mdata = vortex_afu_->af2cp_sTxPort_c1_hdr_mdata;
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auto host_ptr = this->find_host_ptr(vortex_afu_->af2cp_sTxPort_c1_hdr_address);
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memcpy(host_ptr, vortex_afu_->af2cp_sTxPort_c1_data, GLOBAL_BLOCK_SIZE);
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cci_writes_.push_back(cci_req);
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}
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}
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void opae_sim::avs_bus() {
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// schedule DRAM read responses
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int dram_rd_index = -1;
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for (int i = 0; i < dram_reads_.size(); i++) {
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if (dram_reads_[i].cycles_left > 0) {
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dram_reads_[i].cycles_left -= 1;
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}
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if ((dram_rd_index == -1)
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&& (dram_reads_[i].cycles_left == 0)) {
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dram_rd_index = i;
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}
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}
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// send DRAM response
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vortex_afu_->avs_readdatavalid = 0;
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if (dram_rd_index != -1) {
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vortex_afu_->avs_readdatavalid = 1;
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memcpy(vortex_afu_->avs_readdata, dram_reads_[dram_rd_index].block.data(), GLOBAL_BLOCK_SIZE);
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dram_reads_.erase(dram_reads_.begin() + dram_rd_index);
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}
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// handle DRAM stalls
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bool dram_stalled = false;
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#ifdef ENABLE_DRAM_STALLS
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if (0 == ((timestamp/2) % DRAM_STALLS_MODULO)) {
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dram_stalled = true;
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} else
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if (dram_reads_.size() >= DRAM_RQ_SIZE) {
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dram_stalled = true;
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}
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#endif
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// process DRAM requests
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if (!dram_stalled) {
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if (vortex_afu_->avs_write) {
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assert(0 == vortex_afu_->mem_bank_select);
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uint64_t byteen = vortex_afu_->avs_byteenable;
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unsigned base_addr = (vortex_afu_->avs_address * GLOBAL_BLOCK_SIZE);
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uint8_t* data = (uint8_t*)(vortex_afu_->avs_writedata);
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for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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ram_[base_addr + i] = data[i];
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}
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}
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}
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if (vortex_afu_->avs_read) {
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assert(0 == vortex_afu_->mem_bank_select);
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dram_rd_req_t dram_req;
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dram_req.cycles_left = DRAM_LATENCY;
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ram_.read(vortex_afu_->avs_address * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.block.data());
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dram_reads_.push_back(dram_req);
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}
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}
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vortex_afu_->avs_waitrequest = dram_stalled;
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}
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uint8_t* opae_sim::find_host_ptr(uint64_t addr) {
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auto b_addr = addr * GLOBAL_BLOCK_SIZE;
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for (auto& host_alloc : host_allocs_) {
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auto alloc_addr = (intptr_t)host_alloc.data;
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if (b_addr >= alloc_addr
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&& b_addr < (alloc_addr + host_alloc.size)) {
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return (uint8_t*)b_addr;
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}
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}
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assert(false);
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return nullptr;
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}
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