diff --git a/hw/rtl/tex_unit/VX_tex_addr.v b/hw/rtl/tex_unit/VX_tex_addr.v index c1d727a7..af96e0f9 100644 --- a/hw/rtl/tex_unit/VX_tex_addr.v +++ b/hw/rtl/tex_unit/VX_tex_addr.v @@ -151,8 +151,8 @@ module VX_tex_addr #( end for (genvar i = 0; i < `NUM_THREADS; ++i) begin - assign blend_u[i] = clamped_u_s0[i][0][`BLEND_FRAC-1:0]; - assign blend_v[i] = clamped_v_s0[i][0][`BLEND_FRAC-1:0]; + assign blend_u[i] = filter_s0 ? clamped_u_s0[i][0][`BLEND_FRAC-1:0] : `BLEND_FRAC'(0); + assign blend_v[i] = filter_s0 ? clamped_v_s0[i][0][`BLEND_FRAC-1:0] : `BLEND_FRAC'(0); end assign stall_out = rsp_valid && ~rsp_ready; diff --git a/hw/rtl/tex_unit/VX_tex_define.vh b/hw/rtl/tex_unit/VX_tex_define.vh index e88d3fb1..2b87d4da 100644 --- a/hw/rtl/tex_unit/VX_tex_define.vh +++ b/hw/rtl/tex_unit/VX_tex_define.vh @@ -5,7 +5,7 @@ `define FIXED_FRAC 20 `define FIXED_INT (32 - `FIXED_FRAC) -`define FIXED_ONE (1 << `FIXED_FRAC) +`define FIXED_ONE (2 ** `FIXED_FRAC) `define FIXED_HALF (`FIXED_ONE >> 1) `define FIXED_MASK (`FIXED_ONE - 1) @@ -28,7 +28,9 @@ `define TEX_WRAP_MIRROR 2 `define TEX_COLOR_BITS 8 + `define BLEND_FRAC 8 +`define BLEND_ONE (2 ** `BLEND_FRAC) `define TEX_FORMAT_R8G8B8A8 `TEX_FORMAT_BITS'(0) `define TEX_FORMAT_R5G6B5 `TEX_FORMAT_BITS'(1) diff --git a/hw/rtl/tex_unit/VX_tex_lerp.v b/hw/rtl/tex_unit/VX_tex_lerp.v index 07a6afb4..5495688e 100644 --- a/hw/rtl/tex_unit/VX_tex_lerp.v +++ b/hw/rtl/tex_unit/VX_tex_lerp.v @@ -8,8 +8,8 @@ module VX_tex_lerp #( output wire [31:0] out ); for (genvar i = 0; i < 4; ++i) begin - wire [8:0] m1 = (8'hff - blend); - wire [16:0] sum = in1[i*8+:8] * blend + in2[i*8+:8] * m1; + wire [8:0] blend_m1 = `BLEND_ONE - blend; + wire [16:0] sum = in1[i*8+:8] * blend_m1 + in2[i*8+:8] * blend; `UNUSED_VAR (sum) assign out[i*8+:8] = sum[15:8]; end diff --git a/hw/rtl/tex_unit/VX_tex_sampler.v b/hw/rtl/tex_unit/VX_tex_sampler.v index f912631c..6b06eb95 100644 --- a/hw/rtl/tex_unit/VX_tex_sampler.v +++ b/hw/rtl/tex_unit/VX_tex_sampler.v @@ -35,7 +35,7 @@ module VX_tex_sampler #( wire [`NUM_THREADS-1:0][31:0] texel_ul, texel_uh; wire [`NUM_THREADS-1:0][31:0] texel_ul_s0, texel_uh_s0; - wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] blend_v_qual, blend_v_s0; + wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] blend_v_s0; wire [`NUM_THREADS-1:0][31:0] texel_v; wire req_valid_s0; @@ -49,8 +49,7 @@ module VX_tex_sampler #( for (genvar i = 0; i < `NUM_THREADS; i++) begin - wire [3:0][31:0] fmt_texels; - wire [31:0] texel_ul_unqual; + wire [3:0][31:0] fmt_texels; for (genvar j = 0; j < 4; j++) begin VX_tex_format #( @@ -67,7 +66,7 @@ module VX_tex_sampler #( .blend (req_blend_u[i]), .in1 (fmt_texels[0]), .in2 (fmt_texels[1]), - .out (texel_ul_unqual) + .out (texel_ul[i]) ); VX_tex_lerp #( @@ -76,10 +75,7 @@ module VX_tex_sampler #( .in1 (fmt_texels[2]), .in2 (fmt_texels[3]), .out (texel_uh[i]) - ); - - assign blend_v_qual[i] = req_filter ? `BLEND_FRAC'(0) : req_blend_v[i]; - assign texel_ul[i] = req_filter ? fmt_texels[0] : texel_ul_unqual; + ); end VX_pipe_register #( @@ -89,8 +85,8 @@ module VX_tex_sampler #( .clk (clk), .reset (reset), .enable (~stall_out), - .data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, blend_v_qual, texel_ul, texel_uh}), - .data_out ({req_valid_s0, req_wid_s0, req_tmask_s0, req_PC_s0, req_rd_s0, req_wb_s0, blend_v_s0, texel_ul_s0, texel_uh_s0}) + .data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_blend_v, texel_ul, texel_uh}), + .data_out ({req_valid_s0, req_wid_s0, req_tmask_s0, req_PC_s0, req_rd_s0, req_wb_s0, blend_v_s0, texel_ul_s0, texel_uh_s0}) ); for (genvar i = 0; i < `NUM_THREADS; i++) begin