read and write complete

This commit is contained in:
trmontgomery
2020-07-13 23:48:51 -04:00
parent e155c8a9b3
commit 0e8b9ec1c2
40 changed files with 45511 additions and 58479 deletions

BIN
hw/unit_tests/cache/obj_dir/VVX_cache vendored Executable file

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@@ -33,14 +33,15 @@ VM_PREFIX = VVX_cache
VM_MODPREFIX = VVX_cache
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DWORD_SIZE=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 \
-std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
cache_sim \
cachesim \
testbench \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
@@ -56,7 +57,9 @@ include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
cache_sim.o: cache_sim.cpp
cachesim.o: cachesim.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
testbench.o: testbench.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)

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@@ -0,0 +1,3 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "VVX_cache.cpp"

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@@ -0,0 +1,4 @@
VVX_cache__ALLcls.o: VVX_cache__ALLcls.cpp VVX_cache.cpp VVX_cache.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h

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@@ -0,0 +1,5 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "VVX_cache__Trace.cpp"
#include "VVX_cache__Syms.cpp"
#include "VVX_cache__Trace__Slow.cpp"

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@@ -0,0 +1,6 @@
VVX_cache__ALLsup.o: VVX_cache__ALLsup.cpp VVX_cache__Trace.cpp \
/usr/local/share/verilator/include/verilated_vcd_c.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated.h VVX_cache__Syms.h \
/usr/local/share/verilator/include/verilated_heavy.h VVX_cache.h \
VVX_cache__Syms.cpp VVX_cache__Trace__Slow.cpp

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@@ -22,8 +22,6 @@ VVX_cache__Syms::VVX_cache__Syms(VVX_cache* topp, const char* namep)
// Setup scopes
__Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue", "dfqq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.prfqq.pfq_queue", "pfq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.prfqq.pfq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[0].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
@@ -64,44 +62,4 @@ VVX_cache__Syms::VVX_cache__Syms(VVX_cache* topp, const char* namep)
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[4].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[4].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[4].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[4].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[4].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[5].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[5].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[5].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[5].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[5].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[6].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[6].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[6].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[6].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[6].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[7].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[7].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[7].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[7].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[7].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
}

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@@ -27,8 +27,6 @@ class VVX_cache__Syms : public VerilatedSyms {
// SCOPE NAMES
VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue;
VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue;
VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue;
@@ -69,46 +67,6 @@ class VVX_cache__Syms : public VerilatedSyms {
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue__genblk3__genblk2;
// CREATORS
VVX_cache__Syms(VVX_cache* topp, const char* namep);

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@@ -0,0 +1 @@
obj_dir/VVX_cache.cpp obj_dir/VVX_cache.h obj_dir/VVX_cache.mk obj_dir/VVX_cache__Syms.cpp obj_dir/VVX_cache__Syms.h obj_dir/VVX_cache__Trace.cpp obj_dir/VVX_cache__Trace__Slow.cpp obj_dir/VVX_cache__ver.d obj_dir/VVX_cache_classes.mk : /usr/local/bin/verilator_bin ../../rtl//VX_config.vh ../../rtl//VX_define.vh ../../rtl//VX_scope.vh ../../rtl//VX_user_config.vh ../../rtl/cache/VX_bank.v ../../rtl/cache/VX_bank_core_req_arb.v ../../rtl/cache/VX_cache.v ../../rtl/cache/VX_cache_config.vh ../../rtl/cache/VX_cache_core_req_bank_sel.v ../../rtl/cache/VX_cache_core_rsp_merge.v ../../rtl/cache/VX_cache_dram_fill_arb.v ../../rtl/cache/VX_cache_dram_req_arb.v ../../rtl/cache/VX_cache_miss_resrv.v ../../rtl/cache/VX_prefetcher.v ../../rtl/cache/VX_snp_forwarder.v ../../rtl/cache/VX_snp_rsp_arb.v ../../rtl/cache/VX_tag_data_access.v ../../rtl/cache/VX_tag_data_structure.v ../../rtl/libs/VX_fair_arbiter.v ../../rtl/libs/VX_fixed_arbiter.v ../../rtl/libs/VX_generic_queue.v ../../rtl/libs/VX_generic_register.v ../../rtl/libs/VX_indexable_queue.v ../../rtl/libs/VX_priority_encoder.v /usr/local/bin/verilator_bin

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@@ -0,0 +1,37 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--language 1800-2009 --assert -Wall --trace -Wno-DECLFILENAME --x-initial unique -exe cachesim.cpp testbench.cpp -I../../rtl/ -I../../rtl/cache -I../../rtl/libs -DNDEBUG -cc VX_cache.v -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 -CFLAGS -std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 --exe cachesim.cpp testbench.cpp"
S 6992 4983715 1593571269 845187304 1593571269 845187304 "../../rtl//VX_config.vh"
S 8927 4983721 1593571269 845187304 1593571269 845187304 "../../rtl//VX_define.vh"
S 16028 4983736 1593571269 849188141 1593571269 849188141 "../../rtl//VX_scope.vh"
S 147 4980795 1592347024 921834494 1592347024 921834494 "../../rtl//VX_user_config.vh"
S 34555 4983741 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_bank.v"
S 6128 4983742 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_bank_core_req_arb.v"
S 22942 4985366 1594500482 317211549 1594500482 317211549 "../../rtl/cache/VX_cache.v"
S 2842 4983744 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_config.vh"
S 1745 4983745 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_core_req_bank_sel.v"
S 3719 4983746 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_core_rsp_merge.v"
S 3602 4983747 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_dram_fill_arb.v"
S 4396 4985343 1593571951 15994059 1593571951 7993214 "../../rtl/cache/VX_cache_dram_req_arb.v"
S 7305 4983749 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_miss_resrv.v"
S 1996 4983748 1593571988 408039126 1593571988 396037801 "../../rtl/cache/VX_prefetcher.v"
S 5064 4983751 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_snp_forwarder.v"
S 1210 4983752 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_snp_rsp_arb.v"
S 8840 4983753 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_access.v"
S 3211 4983754 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_structure.v"
S 1865 4983777 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_fair_arbiter.v"
S 1022 4983778 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_fixed_arbiter.v"
S 5974 4983779 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_generic_queue.v"
S 582 4983780 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_generic_register.v"
S 1552 4983782 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_indexable_queue.v"
S 491 4983785 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_priority_encoder.v"
S 8183216 2503059 1591812755 756668753 1591812755 756668753 "/usr/local/bin/verilator_bin"
T 3001929 4983824 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache.cpp"
T 93468 4983825 1594500491 473600112 1594500491 473600112 "obj_dir/VVX_cache.h"
T 2104 4983826 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache.mk"
T 8694 4983827 1594500491 449599094 1594500491 449599094 "obj_dir/VVX_cache__Syms.cpp"
T 4866 4983828 1594500491 449599094 1594500491 449599094 "obj_dir/VVX_cache__Syms.h"
T 429460 4983829 1594500491 469599943 1594500491 469599943 "obj_dir/VVX_cache__Trace.cpp"
T 700979 4983830 1594500491 461599603 1594500491 461599603 "obj_dir/VVX_cache__Trace__Slow.cpp"
T 1118 4980960 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache__ver.d"
T 0 0 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache__verFiles.dat"
T 1315 4983831 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache_classes.mk"

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cache_sim.o: ../cache_sim.cpp VVX_cache.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \
VVX_cache.h /usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_vcd_c.h

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cachesim.o: ../cachesim.cpp ../cachesim.h VVX_cache.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \
VVX_cache.h /usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_vcd_c.h ../ram.h

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testbench.o: ../testbench.cpp ../cachesim.h VVX_cache.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \
VVX_cache.h /usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_vcd_c.h ../ram.h

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verilated.o: /usr/local/share/verilator/include/verilated.cpp \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_imp.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated_syms.h \
/usr/local/share/verilator/include/verilated_sym_props.h \
/usr/local/share/verilator/include/verilated_config.h

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verilated_vcd_c.o: /usr/local/share/verilator/include/verilated_vcd_c.cpp \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_vcd_c.h

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