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bank deadlock fix

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This commit is contained in:
Blaise Tine
2021-01-13 15:51:42 -08:00
parent 79cc4d98e6
commit 0e1650e1c2
1 changed files with 11 additions and 4 deletions
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15
hw/rtl/cache/VX_bank.v vendored
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@@ -238,11 +238,12 @@ module VX_bank #(
wire is_mshr_miss_st1 = valid_st1 && is_mshr_st1 && (miss_st1 || force_miss_st1); wire is_mshr_miss_st1 = valid_st1 && is_mshr_st1 && (miss_st1 || force_miss_st1);
// determine which queue to pop next in piority order // determine which queue to pop next in piority order
wire mshr_pop_unqual = mshr_valid && !is_mshr_miss_st1; wire mshr_pop_unqual = mshr_valid;
wire drsq_pop_unqual = !mshr_pop_unqual && !drsq_empty; wire drsq_pop_unqual = !mshr_pop_unqual && !drsq_empty;
wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty && !mshr_almost_full && !dreq_almost_full; wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty && !mshr_almost_full && !dreq_almost_full;
assign mshr_pop = mshr_pop_unqual && !pipeline_stall; assign mshr_pop = mshr_pop_unqual && !pipeline_stall
&& !is_mshr_miss_st1; // do not schedule another mshr request when the previous one missed
assign drsq_pop = drsq_pop_unqual && !pipeline_stall; assign drsq_pop = drsq_pop_unqual && !pipeline_stall;
assign creq_pop = creq_pop_unqual && !pipeline_stall; assign creq_pop = creq_pop_unqual && !pipeline_stall;
@@ -270,6 +271,12 @@ module VX_bank #(
.data_out ({addr_st0, wsel_st0, mem_rw_st0, byteen_st0, writeword_st0, req_tid_st0, tag_st0, filldata_st0}) .data_out ({addr_st0, wsel_st0, mem_rw_st0, byteen_st0, writeword_st0, req_tid_st0, tag_st0, filldata_st0})
); );
always @(posedge clk) begin
/*if (valid_st0) begin
if (mshr_pop)
end*/
end
`ifdef DBG_CACHE_REQ_INFO `ifdef DBG_CACHE_REQ_INFO
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st0, debug_wid_st0} = tag_st0[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS]; assign {debug_pc_st0, debug_wid_st0} = tag_st0[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
@@ -477,7 +484,7 @@ end
.WORD_SIZE (WORD_SIZE), .WORD_SIZE (WORD_SIZE),
.NUM_REQS (NUM_REQS), .NUM_REQS (NUM_REQS),
.MSHR_SIZE (MSHR_SIZE), .MSHR_SIZE (MSHR_SIZE),
.ALM_FULL (MSHR_SIZE-2), .ALM_FULL (MSHR_SIZE-1),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH) .CORE_TAG_WIDTH (CORE_TAG_WIDTH)
) miss_resrv ( ) miss_resrv (
.clk (clk), .clk (clk),
@@ -628,7 +635,7 @@ end
VX_fifo_queue_xt #( VX_fifo_queue_xt #(
.DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH), .DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (DREQ_SIZE), .SIZE (DREQ_SIZE),
.ALM_FULL (DREQ_SIZE-2), .ALM_FULL (DREQ_SIZE-1),
.FASTRAM (1) .FASTRAM (1)
) dram_req_queue ( ) dram_req_queue (
.clk (clk), .clk (clk),