From 0debdd3fe78f62e3c6f8db6e87034803dbfc144f Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@yahoo.com>
Date: Sun, 8 Aug 2021 02:59:30 -0700
Subject: [PATCH] minor update

---
 hw/rtl/VX_config.vh   |  5 +++++
 hw/rtl/VX_ibuffer.v   | 13 +++++++------
 hw/scripts/scope.json |  2 +-
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh
index e28a41b1..74dc3080 100644
--- a/hw/rtl/VX_config.vh
+++ b/hw/rtl/VX_config.vh
@@ -232,6 +232,11 @@
 
 // Pipeline Queues ////////////////////////////////////////////////////////////
 
+// Size of Instruction Buffer
+`ifndef IBUF_SIZE
+`define IBUF_SIZE 4
+`endif
+
 // Size of LSU Request Queue
 `ifndef LSUQ_SIZE
 `define LSUQ_SIZE (`NUM_WARPS * 2)
diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.v
index 82c1d8a4..28c70ad2 100644
--- a/hw/rtl/VX_ibuffer.v
+++ b/hw/rtl/VX_ibuffer.v
@@ -16,8 +16,7 @@ module VX_ibuffer #(
     `UNUSED_PARAM (CORE_ID)
     
     localparam DATAW   = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS;
-    localparam SIZE    = 3;
-    localparam ADDRW   = $clog2(SIZE);
+    localparam ADDRW   = $clog2(`IBUF_SIZE+1);
     localparam NWARPSW = $clog2(`NUM_WARPS+1);
 
     reg [`NUM_WARPS-1:0][ADDRW-1:0] used_r;
@@ -38,8 +37,9 @@ module VX_ibuffer #(
 
         wire is_head_ptr = empty_r[i] || (alm_empty_r[i] && reading);
 
-        VX_skid_buffer #(
-            .DATAW (DATAW)
+        VX_elastic_buffer #(
+            .DATAW (DATAW),
+            .SIZE  (`IBUF_SIZE)
         ) queue (
             .clk      (clk),
             .reset    (reset),
@@ -63,7 +63,7 @@ module VX_ibuffer #(
                         empty_r[i] <= 0;
                         if (used_r[i] == 1)
                             alm_empty_r[i] <= 0;
-                        if (used_r[i] == ADDRW'(SIZE-1))
+                        if (used_r[i] == ADDRW'(`IBUF_SIZE))
                             full_r[i] <= 1;
                     end
                 end else if (reading) begin
@@ -160,10 +160,11 @@ module VX_ibuffer #(
         end
             
         deq_wid   <= deq_wid_n;
-        deq_instr <= deq_instr_n;     
+        deq_instr <= deq_instr_n;
     end
     
     assign decode_if.ready = ~q_full[decode_if.wid];
+    
     assign q_data_in = {decode_if.tmask, 
                         decode_if.PC, 
                         decode_if.ex_type, 
diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json
index 4c411131..9c0baacd 100644
--- a/hw/scripts/scope.json
+++ b/hw/scripts/scope.json
@@ -138,7 +138,7 @@
             "icache_rsp_tag":"`ICORE_TAG_ID_BITS"
         },
         "afu/vortex/cluster/core/pipeline/fetch/warp_sched": {
-            "?wsched_scheduled_warp": 1,
+            "?wsched_scheduled": 1,
             "wsched_active_warps": "`NUM_WARPS",
             "wsched_stalled_warps": "`NUM_WARPS",
             "wsched_schedule_tmask": "`NUM_THREADS",