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Added schedule_ptr to mrvq for speculative pops

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This commit is contained in:
felsabbagh3
2020-05-23 21:36:57 -07:00
parent c54fa50715
commit 0cd9bd689e
2 changed files with 113 additions and 53 deletions
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39
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@@ -23,6 +23,7 @@ module VX_cache_miss_resrv #(
// Miss enqueue
input wire miss_add,
input wire from_mrvq,
input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
input wire[`BASE_ADDR_BITS-1:0] miss_add_wsel,
input wire[`WORD_WIDTH-1:0] miss_add_data,
@@ -57,6 +58,7 @@ module VX_cache_miss_resrv #(
reg [MRVQ_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
reg [MRVQ_SIZE-1:0] valid_table;
reg [MRVQ_SIZE-1:0] ready_table;
reg [`LOG2UP(MRVQ_SIZE)-1:0] schedule_ptr;
reg [`LOG2UP(MRVQ_SIZE)-1:0] head_ptr;
reg [`LOG2UP(MRVQ_SIZE)-1:0] tail_ptr;
@@ -86,16 +88,21 @@ module VX_cache_miss_resrv #(
assign pending_hazard = |(valid_address_match);
wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr];
wire [`LOG2UP(MRVQ_SIZE)-1:0] dequeue_index = head_ptr;
wire dequeue_possible = valid_table[schedule_ptr] && ready_table[schedule_ptr];
wire [`LOG2UP(MRVQ_SIZE)-1:0] dequeue_index = schedule_ptr;
assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible;
assign miss_resrv_addr_st0 = addr_table[dequeue_index];
assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_tag_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0, miss_resrv_wsel_st0, miss_resrv_is_snp_st0} = metadata_table[dequeue_index];
wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2);
wire mrvq_push = miss_add && enqueue_possible && !from_mrvq && (MRVQ_SIZE != 2);
wire mrvq_pop = miss_resrv_pop && dequeue_possible;
wire recover_state = miss_add && from_mrvq;
wire increment_head = !miss_add && from_mrvq;
wire update_ready = (|make_ready);
wire qual_mrvq_init = mrvq_push && mrvq_init_ready_state;
@@ -105,18 +112,25 @@ module VX_cache_miss_resrv #(
always @(posedge clk) begin
if (reset) begin
valid_table <= 0;
ready_table <= 0;
size <= 0;
head_ptr <= 0;
tail_ptr <= 0;
valid_table <= 0;
ready_table <= 0;
size <= 0;
schedule_ptr <= 0;
head_ptr <= 0;
tail_ptr <= 0;
end else begin
if (mrvq_push) begin
valid_table[enqueue_index] <= 1;
ready_table[enqueue_index] <= mrvq_init_ready_state;
addr_table[enqueue_index] <= miss_add_addr;
metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_wsel, miss_add_is_snp};
tail_ptr <= tail_ptr + 1;
end else if (increment_head) begin
valid_table[head_ptr] <= 0;
head_ptr <= head_ptr + 1;
end else if (recover_state) begin
schedule_ptr <= schedule_ptr - 1;
end
// update entry as 'ready' during DRAM fill response
@@ -125,16 +139,15 @@ module VX_cache_miss_resrv #(
end
if (mrvq_pop) begin
valid_table[dequeue_index] <= 0;
ready_table[dequeue_index] <= 0;
head_ptr <= head_ptr + 1;
schedule_ptr <= schedule_ptr + 1;
end
if (!(mrvq_push && mrvq_pop)) begin
if (!(mrvq_push && increment_head)) begin
if (mrvq_push) begin
size <= size + 1;
end
if (mrvq_pop) begin
if (increment_head) begin
size <= size - 1;
end
end
@@ -149,7 +162,7 @@ module VX_cache_miss_resrv #(
for (j = 0; j < MRVQ_SIZE; j++) begin
if (valid_table[j]) begin
$write(" ");
if (head_ptr == $bits(head_ptr)'(j)) $write("*");
if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
if (~ready_table[j]) $write("!");
$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
end