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opae rtl fixes

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This commit is contained in:
Blaise Tine
2020-05-18 20:19:02 -07:00
parent 11ace25f27
commit 0c88da2bfb
7 changed files with 153 additions and 122 deletions
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2
hw/rtl/VX_csr_pipe.v
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@@ -60,7 +60,7 @@ module VX_csr_pipe #(
.clk (clk),
.reset(reset),
.stall(no_slot_csr),
.flush(0),
.flush(1'b0),
.in ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_csr, csr_req_if.csr_address, csr_read_data , csr_updated_data }),
.out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_read_data_s2, csr_updated_data_s2})
);

24
hw/rtl/VX_dmem_ctrl.v
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@@ -102,16 +102,16 @@ module VX_dmem_ctrl # (
.dram_req_addr (),
.dram_req_data (),
.dram_req_tag (),
.dram_req_ready (0),
.dram_req_ready (1'b0),
// DRAM response
.dram_rsp_valid (0),
.dram_rsp_valid (1'b0),
.dram_rsp_data (0),
.dram_rsp_tag (0),
.dram_rsp_tag (`SDRAM_TAG_WIDTH'(0)),
.dram_rsp_ready (),
// Snoop request
.snp_req_valid (0),
.snp_req_valid (1'b0),
.snp_req_addr (0),
.snp_req_tag (0),
.snp_req_ready (),
@@ -119,7 +119,7 @@ module VX_dmem_ctrl # (
// Snoop response
.snp_rsp_valid (),
.snp_rsp_tag (),
.snp_rsp_ready (0),
.snp_rsp_ready (1'b0),
// Snoop forward out
.snp_fwdout_valid (),
@@ -128,7 +128,7 @@ module VX_dmem_ctrl # (
.snp_fwdout_ready (0),
// Snoop forward in
.snp_fwdin_valid (0),
.snp_fwdin_valid (1'b0),
.snp_fwdin_tag (0),
.snp_fwdin_ready ()
`IGNORE_WARNINGS_END
@@ -209,10 +209,10 @@ module VX_dmem_ctrl # (
.snp_fwdout_valid (),
.snp_fwdout_addr (),
.snp_fwdout_tag (),
.snp_fwdout_ready (0),
.snp_fwdout_ready (1'b0),
// Snoop forward in
.snp_fwdin_valid (0),
.snp_fwdin_valid (1'b0),
.snp_fwdin_tag (0),
.snp_fwdin_ready ()
`IGNORE_WARNINGS_END
@@ -278,7 +278,7 @@ module VX_dmem_ctrl # (
`IGNORE_WARNINGS_BEGIN
// Snoop request
.snp_req_valid (0),
.snp_req_valid (1'b0),
.snp_req_addr (0),
.snp_req_tag (0),
.snp_req_ready (),
@@ -286,16 +286,16 @@ module VX_dmem_ctrl # (
// Snoop response
.snp_rsp_valid (),
.snp_rsp_tag (),
.snp_rsp_ready (0),
.snp_rsp_ready (1'b0),
// Snoop forward out
.snp_fwdout_valid (),
.snp_fwdout_addr (),
.snp_fwdout_tag (),
.snp_fwdout_ready (0),
.snp_fwdout_ready (1'b0),
// Snoop forward in
.snp_fwdin_valid (0),
.snp_fwdin_valid (1'b0),
.snp_fwdin_tag (0),
.snp_fwdin_ready ()
`IGNORE_WARNINGS_END

2
hw/rtl/VX_lsu_unit.v
View File

@@ -42,7 +42,7 @@ module VX_lsu_unit #(
.clk (clk),
.reset(reset),
.stall(delay),
.flush(0),
.flush(1'b0),
.in ({address , lsu_req_if.store_data, lsu_req_if.valid, lsu_req_if.mem_read, lsu_req_if.mem_write, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.lsu_pc}),
.out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc })
);

6
hw/rtl/cache/VX_bank.v vendored
View File

@@ -349,7 +349,7 @@ module VX_bank #(
.clk (clk),
.reset (reset),
.stall (stall_bank_pipe),
.flush (0),
.flush (1'b0),
.in ({qual_from_mrvq_st0, qual_is_snp_st0, qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_wsel_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}),
.out ({from_mrvq_st1[0] , is_snp_st1[0], going_to_write_st1[0], valid_st1[0], addr_st1[0], wsel_st1[0], writeword_st1[0], inst_meta_st1[0], is_fill_st1[0], writedata_st1[0]})
);
@@ -362,7 +362,7 @@ module VX_bank #(
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.flush(1'b0),
.in ({from_mrvq_st1[i-1], is_snp_st1[i-1], going_to_write_st1[i-1], valid_st1[i-1], addr_st1[i-1], wsel_st1[i-1], writeword_st1[i-1], inst_meta_st1[i-1], is_fill_st1[i-1], writedata_st1[i-1]}),
.out ({from_mrvq_st1[i] , is_snp_st1[i], going_to_write_st1[i], valid_st1[i], addr_st1[i], wsel_st1[i], writeword_st1[i], inst_meta_st1[i], is_fill_st1[i], writedata_st1[i]})
);
@@ -467,7 +467,7 @@ module VX_bank #(
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.flush(1'b0),
.in ({mrvq_init_ready_state_st1e, snp_to_mrvq_st1e, is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
);

4
hw/rtl/cache/VX_tag_data_access.v vendored
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@@ -111,7 +111,7 @@ module VX_tag_data_access #(
.clk (clk),
.reset(reset),
.stall(stall),
.flush(0),
.flush(1'b0),
.in({qual_read_valid_st1, qual_read_dirty_st1, qual_read_tag_st1, qual_read_data_st1}),
.out({read_valid_st1c[0], read_dirty_st1c[0], read_tag_st1c[0], read_data_st1c[0]})
);
@@ -124,7 +124,7 @@ module VX_tag_data_access #(
.clk (clk),
.reset(reset),
.stall(stall),
.flush(0),
.flush(1'b0),
.in({read_valid_st1c[i-1], read_dirty_st1c[i-1], read_tag_st1c[i-1], read_data_st1c[i-1]}),
.out({read_valid_st1c[i], read_dirty_st1c[i], read_tag_st1c[i], read_data_st1c[i]})
);