lots of errors
This commit is contained in:
felsabbagh3
@@ -20,93 +20,28 @@ using namespace std;
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/* It is important that this stays consistent with the Harp::Instruction::Opcode
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enum. */
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Instruction::InstTableEntry Instruction::instTable[] = {
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//str cflow relad allsrc priv argcl itype
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{"nop", false, false, false, false, AC_NONE, ITYPE_NULL },
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{"di", false, false, false, true, AC_NONE, ITYPE_NULL },
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{"ei", false, false, false, true, AC_NONE, ITYPE_NULL },
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{"tlbadd", false, false, true, true, AC_3REGSRC, ITYPE_NULL },
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{"tlbflush", false, false, false, true, AC_NONE, ITYPE_NULL },
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{"neg", false, false, false, false, AC_2REG, ITYPE_INTBASIC},
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{"not", false, false, false, false, AC_2REG, ITYPE_INTBASIC},
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{"and", false, false, false, false, AC_3REG, ITYPE_INTBASIC},
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{"or", false, false, false, false, AC_3REG, ITYPE_INTBASIC},
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{"xor", false, false, false, false, AC_3REG, ITYPE_INTBASIC},
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{"add", false, false, false, false, AC_3REG, ITYPE_INTBASIC},
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{"sub", false, false, false, false, AC_3REG, ITYPE_INTBASIC},
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{"mul", false, false, false, false, AC_3REG, ITYPE_INTMUL },
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{"div", false, false, false, false, AC_3REG, ITYPE_INTDIV },
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{"mod", false, false, false, false, AC_3REG, ITYPE_INTDIV },
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{"shl", false, false, false, false, AC_3REG, ITYPE_INTBASIC},
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{"shr", false, false, false, false, AC_3REG, ITYPE_INTBASIC},
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{"andi", false, false, false, false, AC_3IMM, ITYPE_INTBASIC},
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{"ori", false, false, false, false, AC_3IMM, ITYPE_INTBASIC},
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{"xori", false, false, false, false, AC_3IMM, ITYPE_INTBASIC},
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{"addi", false, false, false, false, AC_3IMM, ITYPE_INTBASIC},
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{"subi", false, false, false, false, AC_3IMM, ITYPE_INTBASIC},
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{"muli", false, false, false, false, AC_3IMM, ITYPE_INTMUL },
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{"divi", false, false, false, false, AC_3IMM, ITYPE_INTDIV },
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{"modi", false, false, false, false, AC_3IMM, ITYPE_INTDIV },
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{"shli", false, false, false, false, AC_3IMM, ITYPE_INTBASIC},
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{"shri", false, false, false, false, AC_3IMM, ITYPE_INTBASIC},
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{"jali", true, true, false, false, AC_2IMM, ITYPE_CALL },
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{"jalr", true, false, false, false, AC_2REG, ITYPE_CALL },
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{"jmpi", true, true, true, false, AC_1IMM, ITYPE_BR },
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{"jmpr", true, false, true, false, AC_1REG, ITYPE_RET },
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{"clone", true, false, false, false, AC_1REG, ITYPE_NULL },
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{"jalis", true, true, false, false, AC_3IMM, ITYPE_CALL },
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{"jalrs", true, false, false, false, AC_3REG, ITYPE_CALL },
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{"jmprt", true, false, true, false, AC_1REG, ITYPE_RET },
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{"ld", false, false, false, false, AC_3IMM, ITYPE_NULL },
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{"st", false, false, true, false, AC_3IMMSRC, ITYPE_NULL },
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{"ldi", false, false, false, false, AC_2IMM, ITYPE_NULL },
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{"rtop", false, false, false, false, AC_PREG_REG, ITYPE_NULL },
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{"andp", false, false, false, false, AC_3PREG, ITYPE_INTBASIC},
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{"orp", false, false, false, false, AC_3PREG, ITYPE_INTBASIC},
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{"xorp", false, false, false, false, AC_3PREG, ITYPE_INTBASIC},
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{"notp", false, false, false, false, AC_2PREG, ITYPE_INTBASIC},
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{"isneg", false, false, false, false, AC_PREG_REG, ITYPE_INTBASIC},
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{"iszero", false, false, false, false, AC_PREG_REG, ITYPE_INTBASIC},
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{"halt", false, false, false, false, AC_NONE, ITYPE_NULL },
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{"trap", true, false, false, false, AC_NONE, ITYPE_TRAP },
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{"jmpru", false, false, false, true, AC_1REG, ITYPE_RET },
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{"skep", false, false, false, true, AC_1REG, ITYPE_NULL },
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{"reti", true, false, false, true, AC_NONE, ITYPE_RET },
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{"tlbrm", false, false, false, true, AC_1REG, ITYPE_NULL },
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{"itof", false, false, false, false, AC_2REG, ITYPE_FPBASIC },
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{"ftoi", false, false, false, false, AC_2REG, ITYPE_FPBASIC },
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{"fadd", false, false, false, false, AC_3REG, ITYPE_FPBASIC },
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{"fsub", false, false, false, false, AC_3REG, ITYPE_FPBASIC },
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{"fmul", false, false, false, false, AC_3REG, ITYPE_FPMUL },
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{"fdiv", false, false, false, false, AC_3REG, ITYPE_FPDIV },
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{"fneg", false, false, false, false, AC_2REG, ITYPE_FPBASIC },
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{"wspawn", false, false, true, false, AC_3REG, ITYPE_NULL },
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{"split", false, false, true, false, AC_NONE, ITYPE_NULL },
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{"join", false, false, true, false, AC_NONE, ITYPE_NULL },
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{"bar", false, false, true, false, AC_2REGSRC, ITYPE_NULL },
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{NULL,false,false,false,false,AC_NONE,ITYPE_NULL}/////// End of table.
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};
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ostream &Harp::operator<<(ostream& os, Instruction &inst) {
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os << dec;
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if (inst.predicated) {
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os << "@p" << dec << inst.pred << " ? ";
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}
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// if (inst.predicated) {
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// os << "@p" << dec << inst.pred << " ? ";
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// }
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os << Instruction::instTable[inst.op].opString << ' ';
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if (inst.rdestPresent) os << "%r" << dec << inst.rdest << ' ';
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if (inst.pdestPresent) os << "@p" << inst.pdest << ' ';
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for (int i = 0; i < inst.nRsrc; i++) {
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os << "%r" << dec << inst.rsrc[i] << ' ';
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}
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for (int i = 0; i < inst.nPsrc; i++) {
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os << "@p" << dec << inst.psrc[i] << ' ';
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}
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if (inst.immsrcPresent) {
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if (inst.refLiteral) os << inst.refLiteral->name;
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else os << "#0x" << hex << inst.immsrc;
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}
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// os << inst.instTable[inst.op].opString << ' ';
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// if (inst.rdestPresent) os << "%r" << dec << inst.rdest << ' ';
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// if (inst.pdestPresent) os << "@p" << inst.pdest << ' ';
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// for (int i = 0; i < inst.nRsrc; i++) {
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// os << "%r" << dec << inst.rsrc[i] << ' ';
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// }
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// for (int i = 0; i < inst.nPsrc; i++) {
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// os << "@p" << dec << inst.psrc[i] << ' ';
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// }
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// if (inst.immsrcPresent) {
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// if (inst.refLiteral) os << inst.refLiteral->name;
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// else os << "#0x" << hex << inst.immsrc;
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// }
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os << inst.instTable[inst.op].opString;
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os << ';';
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return os;
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@@ -134,6 +69,11 @@ bool checkUnanimous(unsigned p, const std::vector<std::vector<Reg<bool> > >& m,
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return true;
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}
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Word signExt(Word w, Size bit, Word mask) {
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if (w>>(bit-1)) w |= ~mask;
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return w;
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}
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void Instruction::executeOn(Warp &c) {
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D(3, "Begin instruction execute.");
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@@ -165,7 +105,7 @@ void Instruction::executeOn(Warp &c) {
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// If we have a load, overwriting a register's contents, we have to make sure
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// ahead of time it will not fault. Otherwise we may perform an indirect load
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// by mistake.
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if (op == LD && rdest == rsrc[0]) {
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if (op == L_INST && rdest == rsrc[0]) {
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for (Size t = 0; t < c.activeThreads; t++) {
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if ((!predicated || c.pred[t][pred]) && c.tmask[t]) {
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Word memAddr = c.reg[t][rsrc[0]] + immsrc;
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@@ -183,261 +123,341 @@ void Instruction::executeOn(Warp &c) {
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// If this thread is masked out, don't execute the instruction, unless it's
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// a split or join.
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if (((predicated && !pReg[pred]) || !c.tmask[t]) &&
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op != SPLIT && op != JOIN) continue;
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// if (((predicated && !pReg[pred]) || !c.tmask[t]) &&
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// op != SPLIT && op != JOIN) continue;
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++c.insts;
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Word memAddr;
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Word memAddr;
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Word shift_by;
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switch (op) {
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case NOP: break;
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case DI: c.interruptEnable = false;
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break;
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case EI: c.interruptEnable = true;
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break;
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case TLBADD: c.core->mem.tlbAdd(reg[rsrc[0]], reg[rsrc[1]], reg[rsrc[2]]);
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break;
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case TLBFLUSH: c.core->mem.tlbFlush();
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break;
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case ADD: reg[rdest] = reg[rsrc[0]] + reg[rsrc[1]];
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case R_INST:
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switch (func3)
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{
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case 0:
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if (func7)
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{
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reg[rdest] = reg[rsrc[0]] - reg[rsrc[1]];
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reg[rdest].trunc(wordSz);
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break;
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case SUB: reg[rdest] = reg[rsrc[0]] - reg[rsrc[1]];
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}
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else
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{
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reg[rdest] = reg[rsrc[0]] + reg[rsrc[1]];
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reg[rdest].trunc(wordSz);
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break;
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case MUL: reg[rdest] = reg[rsrc[0]] * reg[rsrc[1]];
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}
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break;
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case 1:
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reg[rdest] = reg[rsrc[0]] << reg[rsrc[1]];
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reg[rdest].trunc(wordSz);
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break;
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case DIV: if (reg[rsrc[1]] == 0) throw DomainException();
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reg[rdest] = reg[rsrc[0]] / reg[rsrc[1]];
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break;
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case SHL: reg[rdest] = reg[rsrc[0]] << reg[rsrc[1]];
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break;
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case 2:
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if ( Word_s(reg[rsrc[0]]) < Word_s(reg[rsrc[1]]))
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{
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reg[rdest] = 1;
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}
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else
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{
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reg[rdest] = 0;
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}
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break;
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case 3:
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if ( Word_u(reg[rsrc[0]]) < Word_u(reg[rsrc[1]]))
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{
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reg[rdest] = 1;
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}
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else
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{
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reg[rdest] = 0;
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}
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break;
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case 4:
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reg[rdest] = reg[rsrc[0]] ^ reg[rsrc[1]];
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break;
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case 5:
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if (func7)
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{
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reg[rdest] = Word_s(reg[rsrc[0]]) >> Word_s(reg[rsrc[1]]);
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reg[rdest].trunc(wordSz);
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break;
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case SHR: reg[rdest] = Word_s(reg[rsrc[0]]) >> reg[rsrc[1]];
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}
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else
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{
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reg[rdest] = Word_u(reg[rsrc[0]]) >> Word_u(reg[rsrc[1]]);
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reg[rdest].trunc(wordSz);
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break;
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case MOD: if (reg[rsrc[1]] == 0) throw DomainException();
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reg[rdest] = reg[rsrc[0]] % reg[rsrc[1]];
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break;
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case AND: reg[rdest] = reg[rsrc[0]] & reg[rsrc[1]];
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break;
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case OR: reg[rdest] = reg[rsrc[0]] | reg[rsrc[1]];
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break;
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case XOR: reg[rdest] = reg[rsrc[0]] ^ reg[rsrc[1]];
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break;
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case NEG: reg[rdest] = -(Word_s)reg[rsrc[0]];
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reg[rdest].trunc(wordSz);
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break;
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case NOT: reg[rdest] = ~(Word_s)reg[rsrc[0]];
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reg[rdest].trunc(wordSz);
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break;
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case ADDI: reg[rdest] = reg[rsrc[0]] + immsrc;
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reg[rdest].trunc(wordSz);
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break;
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case SUBI: reg[rdest] = reg[rsrc[0]] - immsrc;
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reg[rdest].trunc(wordSz);
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break;
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case MULI: reg[rdest] = reg[rsrc[0]] * immsrc;
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reg[rdest].trunc(wordSz);
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break;
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case DIVI: if (immsrc == 0) throw DomainException();
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reg[rdest] = reg[rsrc[0]] / immsrc;
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break;
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case MODI: if (immsrc == 0) throw DomainException();
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reg[rdest] = reg[rsrc[0]] % immsrc;
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break;
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case SHRI: reg[rdest] = Word_s(reg[rsrc[0]]) >> immsrc;
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break;
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case SHLI: reg[rdest] = reg[rsrc[0]] << immsrc;
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reg[rdest].trunc(wordSz);
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break;
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case ANDI: reg[rdest] = reg[rsrc[0]] & immsrc;
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break;
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case ORI: reg[rdest] = reg[rsrc[0]] | immsrc;
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break;
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case XORI: reg[rdest] = reg[rsrc[0]] ^ immsrc;
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break;
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case JMPI: if (!pcSet) nextPc = c.pc + immsrc;
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pcSet = true;
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break;
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case JALI: reg[rdest] = c.pc;
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if (!pcSet) nextPc = c.pc + immsrc;
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pcSet = true;
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break;
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case JALR: reg[rdest] = c.pc;
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if (!pcSet) nextPc = reg[rsrc[0]];
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pcSet = true;
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break;
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case JMPR: if (!pcSet) nextPc = reg[rsrc[0]];
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pcSet = true;
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break;
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case CLONE: c.reg[reg[rsrc[0]]] = reg;
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break;
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case JALIS: nextActiveThreads = reg[rsrc[0]];
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reg[rdest] = c.pc;
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if (!pcSet) nextPc = c.pc + immsrc;
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pcSet = true;
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break;
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case JALRS: nextActiveThreads = reg[rsrc[0]];
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reg[rdest] = c.pc;
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if (!pcSet) nextPc = reg[rsrc[1]];
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pcSet = true;
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break;
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case JMPRT: nextActiveThreads = 1;
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if (!pcSet) nextPc = reg[rsrc[0]];
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pcSet = true;
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break;
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case LD: ++c.loads;
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memAddr = reg[rsrc[0]] + immsrc;
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}
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break;
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case 6:
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reg[rdest] = reg[rsrc[0]] | reg[rsrc[1]];
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break;
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case 7:
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reg[rdest] = reg[rsrc[0]] & reg[rsrc[1]];
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break;
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default:
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cout << "ERROR: UNSUPPORTED R INST\n";
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exit(1);
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}
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break;
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case L_INST:
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memAddr = (reg[rsrc[0]] + immsrc) & 0xFFFFFF00;
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shift_by = (reg[rsrc[0]] + immsrc) & 0x000000FF;
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#ifdef EMU_INSTRUMENTATION
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Harp::OSDomain::osDomain->
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do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
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Harp::OSDomain::osDomain->
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do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
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#endif
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reg[rdest] = c.core->mem.read(memAddr, c.supervisorMode);
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c.memAccesses.push_back(Warp::MemAccess(false, memAddr));
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break;
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case ST: ++c.stores;
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memAddr = reg[rsrc[1]] + immsrc;
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c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode);
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c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
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#ifdef EMU_INSTRUMENTATION
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Harp::OSDomain::osDomain->
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do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
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#endif
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break;
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case LDI: reg[rdest] = immsrc;
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reg[rdest].trunc(wordSz);
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break;
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case RTOP: pReg[pdest] = reg[rsrc[0]];
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break;
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case ISZERO: pReg[pdest] = !reg[rsrc[0]];
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break;
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case NOTP: pReg[pdest] = !(pReg[psrc[0]]);
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break;
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case ANDP: pReg[pdest] = pReg[psrc[0]] & pReg[psrc[1]];
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break;
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case ORP: pReg[pdest] = pReg[psrc[0]] | pReg[psrc[1]];
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break;
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case XORP: pReg[pdest] = pReg[psrc[0]] != pReg[psrc[1]];
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break;
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case ISNEG: pReg[pdest] = (1ll<<(wordSz*8 - 1))®[rsrc[0]];
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break;
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case HALT: c.activeThreads = 0;
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nextActiveThreads = 0;
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break;
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case TRAP: c.interrupt(0);
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break;
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case JMPRU: c.supervisorMode = false;
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if (!pcSet) nextPc = reg[rsrc[0]];
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pcSet = true;
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break;
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case SKEP: c.core->interruptEntry = reg[rsrc[0]];
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break;
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case RETI: if (t == 0) {
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c.tmask = c.shadowTmask;
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nextActiveThreads = c.shadowActiveThreads;
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c.interruptEnable = c.shadowInterruptEnable;
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c.supervisorMode = c.shadowSupervisorMode;
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for (unsigned i = 0; i < reg.size(); ++i)
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reg[i] = c.shadowReg[i];
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for (unsigned i = 0; i < pReg.size(); ++i)
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pReg[i] = c.shadowPReg[i];
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if (!pcSet) { nextPc = c.shadowPc; pcSet = true; }
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}
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break;
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case ITOF: reg[rdest] = Float(double(Word_s(reg[rsrc[0]])), wordSz);
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break;
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case FTOI: reg[rdest] = Word_s(double(Float(reg[rsrc[0]], wordSz)));
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reg[rdest].trunc(wordSz);
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break;
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case FNEG: reg[rdest] = Float(-double(Float(reg[rsrc[0]],wordSz)),wordSz);
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break;
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case FADD: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) +
|
||||
double(Float(reg[rsrc[1]], wordSz)),wordSz);
|
||||
break;
|
||||
case FSUB: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) -
|
||||
double(Float(reg[rsrc[1]], wordSz)),wordSz);
|
||||
break;
|
||||
case FMUL: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) *
|
||||
double(Float(reg[rsrc[1]], wordSz)),wordSz);
|
||||
break;
|
||||
case FDIV: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) /
|
||||
double(Float(reg[rsrc[1]], wordSz)),wordSz);
|
||||
break;
|
||||
case SPLIT: if (sjOnce) {
|
||||
sjOnce = false;
|
||||
if (checkUnanimous(pred, c.pred, c.tmask)) {
|
||||
DomStackEntry e(c.tmask);
|
||||
e.uni = true;
|
||||
c.domStack.push(e);
|
||||
break;
|
||||
}
|
||||
DomStackEntry e(pred, c.pred, c.tmask, c.pc);
|
||||
c.domStack.push(c.tmask);
|
||||
c.domStack.push(e);
|
||||
for (unsigned i = 0; i < e.tmask.size(); ++i)
|
||||
c.tmask[i] = !e.tmask[i] && c.tmask[i];
|
||||
}
|
||||
break;
|
||||
case JOIN: if (sjOnce) {
|
||||
sjOnce = false;
|
||||
if (!c.domStack.empty() && c.domStack.top().uni) {
|
||||
D(2, "Uni branch at join");
|
||||
c.tmask = c.domStack.top().tmask;
|
||||
c.domStack.pop();
|
||||
break;
|
||||
}
|
||||
if (!c.domStack.top().fallThrough) {
|
||||
if (!pcSet) nextPc = c.domStack.top().pc;
|
||||
pcSet = true;
|
||||
}
|
||||
c.tmask = c.domStack.top().tmask;
|
||||
c.domStack.pop();
|
||||
}
|
||||
break;
|
||||
case WSPAWN: if (sjOnce) {
|
||||
sjOnce = false;
|
||||
D(0, "Spawning a new warp.");
|
||||
for (unsigned i = 0; i < c.core->w.size(); ++i) {
|
||||
Warp &newWarp(c.core->w[i]);
|
||||
if (newWarp.spawned == false) {
|
||||
newWarp.pc = reg[rsrc[0]];
|
||||
newWarp.reg[0][rdest] = reg[rsrc[1]];
|
||||
newWarp.activeThreads = 1;
|
||||
newWarp.supervisorMode = false;
|
||||
newWarp.spawned = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case BAR: if (sjOnce) {
|
||||
sjOnce = false;
|
||||
Word id(reg[rsrc[0]]), n(reg[rsrc[1]]);
|
||||
set<Warp*> &b(c.core->b[id]);
|
||||
|
||||
// Add current warp to the barrier and halt.
|
||||
b.insert(&c);
|
||||
c.shadowActiveThreads = c.activeThreads;
|
||||
nextActiveThreads = 0;
|
||||
|
||||
D(2, "Barrier " << id << ' ' << b.size() << " of " << n);
|
||||
|
||||
// If the barrier's full, reactivate warps waiting at it
|
||||
if (b.size() == n) {
|
||||
set<Warp*>::iterator it;
|
||||
for (it = b.begin(); it != b.end(); ++it)
|
||||
(*it)->activeThreads = (*it)->shadowActiveThreads;
|
||||
c.core->b.erase(id);
|
||||
nextActiveThreads = c.shadowActiveThreads;
|
||||
}
|
||||
}
|
||||
break;
|
||||
switch (func3)
|
||||
{
|
||||
|
||||
case 0:
|
||||
// LB
|
||||
reg[rdest] = signExt((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFF, 8, 0xFF);
|
||||
break;
|
||||
case 1:
|
||||
// LH
|
||||
reg[rdest] = signExt((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFFFF, 16, 0xFF);
|
||||
break;
|
||||
case 2:
|
||||
reg[rdest] = Word_s(c.core->mem.read(memAddr, c.supervisorMode) & 0xFFFFFFFF);
|
||||
break;
|
||||
case 4:
|
||||
// LBU
|
||||
reg[rdest] = Word_u((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFF);
|
||||
break;
|
||||
case 5:
|
||||
reg[rdest] = Word_s((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFFFF);
|
||||
default:
|
||||
cout << "ERROR: UNSUPPORTED L INST\n";
|
||||
exit(1);
|
||||
c.memAccesses.push_back(Warp::MemAccess(false, memAddr));
|
||||
}
|
||||
break;
|
||||
case I_INST:
|
||||
break;
|
||||
case S_INST:
|
||||
break;
|
||||
case B_INST:
|
||||
break;
|
||||
case LUI_INST:
|
||||
break;
|
||||
case AUIPC_INST:
|
||||
break;
|
||||
case JAL_INST:
|
||||
break;
|
||||
case JALR_INST:
|
||||
break;
|
||||
case SYS_INST:
|
||||
break;
|
||||
default:
|
||||
cout << "ERROR: Unsupported instruction: " << *this << "\n";
|
||||
exit(1);
|
||||
|
||||
|
||||
// case SHL:
|
||||
// break;
|
||||
// case SHR:
|
||||
// break;
|
||||
|
||||
|
||||
|
||||
|
||||
// case ADDI: reg[rdest] = reg[rsrc[0]] + immsrc;
|
||||
// reg[rdest].trunc(wordSz);
|
||||
// break;
|
||||
// case SUBI: reg[rdest] = reg[rsrc[0]] - immsrc;
|
||||
// reg[rdest].trunc(wordSz);
|
||||
// break;
|
||||
|
||||
// case SHRI: reg[rdest] = Word_s(reg[rsrc[0]]) >> immsrc;
|
||||
// break;
|
||||
// case SHLI: reg[rdest] = reg[rsrc[0]] << immsrc;
|
||||
// reg[rdest].trunc(wordSz);
|
||||
// break;
|
||||
// case ANDI: reg[rdest] = reg[rsrc[0]] & immsrc;
|
||||
// break;
|
||||
// case ORI: reg[rdest] = reg[rsrc[0]] | immsrc;
|
||||
// break;
|
||||
// case XORI: reg[rdest] = reg[rsrc[0]] ^ immsrc;
|
||||
// break;
|
||||
// case JMPI: if (!pcSet) nextPc = c.pc + immsrc;
|
||||
// pcSet = true;
|
||||
// break;
|
||||
// case JALI: reg[rdest] = c.pc;
|
||||
// if (!pcSet) nextPc = c.pc + immsrc;
|
||||
// pcSet = true;
|
||||
// break;
|
||||
// case JALR: reg[rdest] = c.pc;
|
||||
// if (!pcSet) nextPc = reg[rsrc[0]];
|
||||
// pcSet = true;
|
||||
// break;
|
||||
// case JMPR: if (!pcSet) nextPc = reg[rsrc[0]];
|
||||
// pcSet = true;
|
||||
// break;
|
||||
|
||||
// case JALIS: nextActiveThreads = reg[rsrc[0]];
|
||||
// reg[rdest] = c.pc;
|
||||
// if (!pcSet) nextPc = c.pc + immsrc;
|
||||
// pcSet = true;
|
||||
// break;
|
||||
// case JALRS: nextActiveThreads = reg[rsrc[0]];
|
||||
// reg[rdest] = c.pc;
|
||||
// if (!pcSet) nextPc = reg[rsrc[1]];
|
||||
// pcSet = true;
|
||||
// break;
|
||||
// case JMPRT: nextActiveThreads = 1;
|
||||
// if (!pcSet) nextPc = reg[rsrc[0]];
|
||||
// pcSet = true;
|
||||
// break;
|
||||
// case LD: ++c.loads;
|
||||
// memAddr = reg[rsrc[0]] + immsrc;
|
||||
// #ifdef EMU_INSTRUMENTATION
|
||||
// Harp::OSDomain::osDomain->
|
||||
// do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
|
||||
// #endif
|
||||
// reg[rdest] = c.core->mem.read(memAddr, c.supervisorMode);
|
||||
// c.memAccesses.push_back(Warp::MemAccess(false, memAddr));
|
||||
// break;
|
||||
// case ST: ++c.stores;
|
||||
// memAddr = reg[rsrc[1]] + immsrc;
|
||||
// c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode);
|
||||
// c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
|
||||
// #ifdef EMU_INSTRUMENTATION
|
||||
// Harp::OSDomain::osDomain->
|
||||
// do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
|
||||
// #endif
|
||||
// break;
|
||||
// case LDI: reg[rdest] = immsrc;
|
||||
// reg[rdest].trunc(wordSz);
|
||||
// break;
|
||||
// case RTOP: pReg[pdest] = reg[rsrc[0]];
|
||||
// break;
|
||||
// case ISZERO: pReg[pdest] = !reg[rsrc[0]];
|
||||
// break;
|
||||
// case NOTP: pReg[pdest] = !(pReg[psrc[0]]);
|
||||
// break;
|
||||
// case ANDP: pReg[pdest] = pReg[psrc[0]] & pReg[psrc[1]];
|
||||
// break;
|
||||
// case ORP: pReg[pdest] = pReg[psrc[0]] | pReg[psrc[1]];
|
||||
// break;
|
||||
// case XORP: pReg[pdest] = pReg[psrc[0]] != pReg[psrc[1]];
|
||||
// break;
|
||||
// case ISNEG: pReg[pdest] = (1ll<<(wordSz*8 - 1))®[rsrc[0]];
|
||||
// break;
|
||||
// case HALT: c.activeThreads = 0;
|
||||
// nextActiveThreads = 0;
|
||||
// break;
|
||||
// case TRAP: c.interrupt(0);
|
||||
// break;
|
||||
// case JMPRU: c.supervisorMode = false;
|
||||
// if (!pcSet) nextPc = reg[rsrc[0]];
|
||||
// pcSet = true;
|
||||
// break;
|
||||
// case SKEP: c.core->interruptEntry = reg[rsrc[0]];
|
||||
// break;
|
||||
// case RETI: if (t == 0) {
|
||||
// c.tmask = c.shadowTmask;
|
||||
// nextActiveThreads = c.shadowActiveThreads;
|
||||
// c.interruptEnable = c.shadowInterruptEnable;
|
||||
// c.supervisorMode = c.shadowSupervisorMode;
|
||||
// for (unsigned i = 0; i < reg.size(); ++i)
|
||||
// reg[i] = c.shadowReg[i];
|
||||
// for (unsigned i = 0; i < pReg.size(); ++i)
|
||||
// pReg[i] = c.shadowPReg[i];
|
||||
// if (!pcSet) { nextPc = c.shadowPc; pcSet = true; }
|
||||
// }
|
||||
// break;
|
||||
// case ITOF: reg[rdest] = Float(double(Word_s(reg[rsrc[0]])), wordSz);
|
||||
// break;
|
||||
// case FTOI: reg[rdest] = Word_s(double(Float(reg[rsrc[0]], wordSz)));
|
||||
// reg[rdest].trunc(wordSz);
|
||||
// break;
|
||||
// case FNEG: reg[rdest] = Float(-double(Float(reg[rsrc[0]],wordSz)),wordSz);
|
||||
// break;
|
||||
// case FADD: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) +
|
||||
// double(Float(reg[rsrc[1]], wordSz)),wordSz);
|
||||
// break;
|
||||
// case FSUB: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) -
|
||||
// double(Float(reg[rsrc[1]], wordSz)),wordSz);
|
||||
// break;
|
||||
// case FMUL: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) *
|
||||
// double(Float(reg[rsrc[1]], wordSz)),wordSz);
|
||||
// break;
|
||||
// case FDIV: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) /
|
||||
// double(Float(reg[rsrc[1]], wordSz)),wordSz);
|
||||
// break;
|
||||
// case SPLIT: if (sjOnce) {
|
||||
// sjOnce = false;
|
||||
// if (checkUnanimous(pred, c.pred, c.tmask)) {
|
||||
// DomStackEntry e(c.tmask);
|
||||
// e.uni = true;
|
||||
// c.domStack.push(e);
|
||||
// break;
|
||||
// }
|
||||
// DomStackEntry e(pred, c.pred, c.tmask, c.pc);
|
||||
// c.domStack.push(c.tmask);
|
||||
// c.domStack.push(e);
|
||||
// for (unsigned i = 0; i < e.tmask.size(); ++i)
|
||||
// c.tmask[i] = !e.tmask[i] && c.tmask[i];
|
||||
// }
|
||||
// break;
|
||||
// case JOIN: if (sjOnce) {
|
||||
// sjOnce = false;
|
||||
// if (!c.domStack.empty() && c.domStack.top().uni) {
|
||||
// D(2, "Uni branch at join");
|
||||
// c.tmask = c.domStack.top().tmask;
|
||||
// c.domStack.pop();
|
||||
// break;
|
||||
// }
|
||||
// if (!c.domStack.top().fallThrough) {
|
||||
// if (!pcSet) nextPc = c.domStack.top().pc;
|
||||
// pcSet = true;
|
||||
// }
|
||||
// c.tmask = c.domStack.top().tmask;
|
||||
// c.domStack.pop();
|
||||
// }
|
||||
// break;
|
||||
// case WSPAWN: if (sjOnce) {
|
||||
// sjOnce = false;
|
||||
// D(0, "Spawning a new warp.");
|
||||
// for (unsigned i = 0; i < c.core->w.size(); ++i) {
|
||||
// Warp &newWarp(c.core->w[i]);
|
||||
// if (newWarp.spawned == false) {
|
||||
// newWarp.pc = reg[rsrc[0]];
|
||||
// newWarp.reg[0][rdest] = reg[rsrc[1]];
|
||||
// newWarp.activeThreads = 1;
|
||||
// newWarp.supervisorMode = false;
|
||||
// newWarp.spawned = true;
|
||||
// break;
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
// break;
|
||||
// case BAR: if (sjOnce) {
|
||||
// sjOnce = false;
|
||||
// Word id(reg[rsrc[0]]), n(reg[rsrc[1]]);
|
||||
// set<Warp*> &b(c.core->b[id]);
|
||||
|
||||
// // Add current warp to the barrier and halt.
|
||||
// b.insert(&c);
|
||||
// c.shadowActiveThreads = c.activeThreads;
|
||||
// nextActiveThreads = 0;
|
||||
|
||||
// D(2, "Barrier " << id << ' ' << b.size() << " of " << n);
|
||||
|
||||
// // If the barrier's full, reactivate warps waiting at it
|
||||
// if (b.size() == n) {
|
||||
// set<Warp*>::iterator it;
|
||||
// for (it = b.begin(); it != b.end(); ++it)
|
||||
// (*it)->activeThreads = (*it)->shadowActiveThreads;
|
||||
// c.core->b.erase(id);
|
||||
// nextActiveThreads = c.shadowActiveThreads;
|
||||
// }
|
||||
// }
|
||||
// break;
|
||||
|
||||
// default:
|
||||
// cout << "ERROR: Unsupported instruction: " << *this << "\n";
|
||||
// exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user