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Implement WU architecture support

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abnerhexu
2026-05-25 19:25:05 +08:00
parent 323ed7d7e9
commit 0ad87bde81
35 changed files with 3303 additions and 472 deletions
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46
hw/rtl/interfaces/VX_pipeline_perf_if.sv
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@@ -17,6 +17,13 @@ interface VX_pipeline_perf_if ();
wire [`PERF_CTR_BITS-1:0] sched_idles;
wire [`PERF_CTR_BITS-1:0] sched_stalls;
wire [`PERF_CTR_BITS-1:0] sched_barrier_idles;
wire [`PERF_CTR_BITS-1:0] scalar_sched_ready_cycles;
wire [`PERF_CTR_BITS-1:0] tensor_sched_ready_cycles;
wire [`PERF_CTR_BITS-1:0] scalar_sched_issued_cycles;
wire [`PERF_CTR_BITS-1:0] tensor_sched_issued_cycles;
wire [`PERF_CTR_BITS-1:0] illegal_tensor_reg_access;
wire [`PERF_CTR_BITS-1:0] illegal_tensor_scalar_op;
wire [`PERF_CTR_BITS-1:0] illegal_scalar_tensor_op;
wire [`PERF_CTR_BITS-1:0] ibf_stalls;
wire [`PERF_CTR_BITS-1:0] scb_stalls;
wire [`PERF_CTR_BITS-1:0] scb_any_unit_uses;
@@ -34,11 +41,26 @@ interface VX_pipeline_perf_if ();
wire [`PERF_CTR_BITS-1:0] stores;
wire [`PERF_CTR_BITS-1:0] ifetch_latency;
wire [`PERF_CTR_BITS-1:0] load_latency;
wire [`PERF_CTR_BITS-1:0] scalar_lsu_reqs;
wire [`PERF_CTR_BITS-1:0] tensor_lsu_reqs;
wire [`PERF_CTR_BITS-1:0] scalar_lsu_stalls;
wire [`PERF_CTR_BITS-1:0] tensor_lsu_stalls;
wire [`PERF_CTR_BITS-1:0] mem_merge_stalls;
modport schedule (
output sched_idles,
output sched_barrier_idles,
output sched_stalls
output sched_stalls,
output scalar_sched_ready_cycles,
output tensor_sched_ready_cycles,
output scalar_sched_issued_cycles,
output tensor_sched_issued_cycles
);
modport decode (
output illegal_tensor_reg_access,
output illegal_tensor_scalar_op,
output illegal_scalar_tensor_op
);
modport issue (
@@ -55,10 +77,25 @@ interface VX_pipeline_perf_if ();
output dispatch_any_fire_cycles
);
modport execute (
output scalar_lsu_reqs,
output tensor_lsu_reqs,
output scalar_lsu_stalls,
output tensor_lsu_stalls,
output mem_merge_stalls
);
modport slave (
input sched_idles,
input sched_barrier_idles,
input sched_stalls,
input scalar_sched_ready_cycles,
input tensor_sched_ready_cycles,
input scalar_sched_issued_cycles,
input tensor_sched_issued_cycles,
input illegal_tensor_reg_access,
input illegal_tensor_scalar_op,
input illegal_scalar_tensor_op,
input ibf_stalls,
input scb_stalls,
input scb_any_unit_uses,
@@ -74,7 +111,12 @@ interface VX_pipeline_perf_if ();
input loads,
input stores,
input ifetch_latency,
input load_latency
input load_latency,
input scalar_lsu_reqs,
input tensor_lsu_reqs,
input scalar_lsu_stalls,
input tensor_lsu_stalls,
input mem_merge_stalls
);
endinterface