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Implement WU architecture support

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This commit is contained in:
abnerhexu
2026-05-25 19:25:05 +08:00
parent 323ed7d7e9
commit 0ad87bde81
35 changed files with 3303 additions and 472 deletions
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33
hw/rtl/core/VX_issue.sv
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@@ -15,7 +15,9 @@
`include "VX_trace.vh"
module VX_issue import VX_gpu_pkg::*; #(
parameter CORE_ID = 0
parameter CORE_ID = 0,
parameter NUM_TENSOR_CORES = `NUM_TENSOR_WARPS,
parameter DOMAIN = WU_DOMAIN_SCALAR
) (
`SCOPE_IO_DECL
@@ -35,9 +37,12 @@ module VX_issue import VX_gpu_pkg::*; #(
VX_dispatch_if.master fpu_dispatch_if [`ISSUE_WIDTH],
`endif
`ifdef EXT_T_ENABLE
VX_dispatch_if.master tensor_alu_dispatch_if [`ISSUE_WIDTH],
VX_dispatch_if.master tensor_lsu_dispatch_if [`ISSUE_WIDTH],
VX_dispatch_if.master tensor_ctrl_dispatch_if [`ISSUE_WIDTH],
VX_dispatch_if.master tensor_dispatch_if [`ISSUE_WIDTH],
`ifdef EXT_T_ASYNC
VX_tc_rf_if.slave tensor_regfile_if,
VX_tc_rf_if.slave tensor_regfile_if[NUM_TENSOR_CORES],
`endif
`endif
VX_dispatch_if.master sfu_dispatch_if [`ISSUE_WIDTH]
@@ -52,7 +57,8 @@ module VX_issue import VX_gpu_pkg::*; #(
`RESET_RELAY (dispatch_reset, reset);
VX_ibuffer #(
.CORE_ID (CORE_ID)
.CORE_ID (CORE_ID),
.DOMAIN (DOMAIN)
) ibuffer (
.clk (clk),
.reset (ibuf_reset),
@@ -61,7 +67,8 @@ module VX_issue import VX_gpu_pkg::*; #(
);
VX_scoreboard #(
.CORE_ID (CORE_ID)
.CORE_ID (CORE_ID),
.DOMAIN (DOMAIN)
) scoreboard (
.clk (clk),
.reset (scoreboard_reset),
@@ -84,7 +91,9 @@ module VX_issue import VX_gpu_pkg::*; #(
VX_operands #(
`endif
.CORE_ID (CORE_ID),
.CACHE_ENABLE (0)
.CACHE_ENABLE (0),
.NUM_TENSOR_CORES (NUM_TENSOR_CORES),
.DOMAIN (DOMAIN)
) operands (
.clk (clk),
.reset (operands_reset),
@@ -99,7 +108,8 @@ module VX_issue import VX_gpu_pkg::*; #(
);
VX_dispatch #(
.CORE_ID (CORE_ID)
.CORE_ID (CORE_ID),
.DOMAIN (DOMAIN)
) dispatch (
.clk (clk),
.reset (dispatch_reset),
@@ -116,11 +126,22 @@ module VX_issue import VX_gpu_pkg::*; #(
.fpu_dispatch_if(fpu_dispatch_if),
`endif
`ifdef EXT_T_ENABLE
.tensor_alu_dispatch_if(tensor_alu_dispatch_if),
.tensor_lsu_dispatch_if(tensor_lsu_dispatch_if),
.tensor_ctrl_dispatch_if(tensor_ctrl_dispatch_if),
.tensor_dispatch_if(tensor_dispatch_if),
`endif
.sfu_dispatch_if(sfu_dispatch_if)
);
wire decode_fire = decode_if.valid && decode_if.ready;
`RUNTIME_ASSERT(
!decode_fire ||
((DOMAIN == WU_DOMAIN_TENSOR) ? `IS_TENSOR_WARP(decode_if.data.wid) : `IS_SCALAR_WARP(decode_if.data.wid)),
("%t: *** core%0d-issue-domain-crossing domain=%0d wid=%0d PC=0x%0h",
$time, CORE_ID, DOMAIN, decode_if.data.wid, decode_if.data.PC)
)
`ifdef SIMULATION
`ifdef DBG_TRACE_CORE_PIPELINE_VCS
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin