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Implement WU architecture support

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This commit is contained in:
abnerhexu
2026-05-25 19:25:05 +08:00
parent 323ed7d7e9
commit 0ad87bde81
35 changed files with 3303 additions and 472 deletions
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30
hw/rtl/core/VX_commit.sv
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@@ -234,6 +234,26 @@ module VX_commit import VX_gpu_pkg::*; #(
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
always @(posedge clk) begin
if (!reset && ($time > `TRACE_STARTTIME)) begin
if ((CORE_ID == 0)
&& commit_if[i].valid
&& ((commit_if[i].data.PC == 32'h80000010) || (commit_if[i].data.PC == 32'h80000014))) begin
`TRACE(1, ("%d: core%0d-commit-arb-out: isw=%0d, valid=%b, ready=%b, wid=%0d, PC=0x%0h, wb=%0d, rd=%0d, tensor=%b, sop=%b, eop=%b, fire=%b (#%0d)\n",
$time, CORE_ID, i, commit_if[i].valid, commit_if[i].ready,
commit_if[i].data.wid, commit_if[i].data.PC,
commit_if[i].data.wb, commit_if[i].data.rd,
commit_if[i].data.tensor, commit_if[i].data.sop,
commit_if[i].data.eop, commit_fire[i], commit_if[i].data.uuid));
end
if ((CORE_ID == 0)
&& writeback_if[i].valid
&& ((writeback_if[i].data.PC == 32'h80000010) || (writeback_if[i].data.PC == 32'h80000014))) begin
`TRACE(1, ("%d: core%0d-writeback-out: isw=%0d, valid=%b, wid=%0d, wis=%0d, PC=0x%0h, rd=%0d, tensor=%b, sop=%b, eop=%b (#%0d)\n",
$time, CORE_ID, i, writeback_if[i].valid,
wis_to_wid(writeback_if[i].data.wis, i), writeback_if[i].data.wis,
writeback_if[i].data.PC, writeback_if[i].data.rd,
writeback_if[i].data.tensor, writeback_if[i].data.sop,
writeback_if[i].data.eop, writeback_if[i].data.uuid));
end
if (alu_commit_if[i].valid && alu_commit_if[i].ready) begin
`TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, alu_commit_if[i].data.wid, alu_commit_if[i].data.PC, alu_commit_if[i].data.tmask, alu_commit_if[i].data.wb, alu_commit_if[i].data.rd, alu_commit_if[i].data.sop, alu_commit_if[i].data.eop));
`TRACE_ARRAY1D(1, alu_commit_if[i].data.data, `NUM_THREADS);
@@ -259,6 +279,16 @@ module VX_commit import VX_gpu_pkg::*; #(
end
end
end
always @(posedge clk) begin
if (!reset && ($time > `TRACE_STARTTIME) && (CORE_ID == 0)) begin
for (integer i = 0; i < `ISSUE_WIDTH; ++i) begin
if (commit_sched_if.committed[i] && (commit_sched_if.committed_wid[i] == `NW_WIDTH'(0))) begin
`TRACE(1, ("%d: core%0d-commit-sched-out: isw=%0d, committed=%b, wid=%0d\n",
$time, CORE_ID, i, commit_sched_if.committed[i], commit_sched_if.committed_wid[i]));
end
end
end
end
`endif
endmodule