minor update
This commit is contained in:
@@ -43,40 +43,40 @@ module VX_io_arb #(
|
||||
input wire [WORD_WIDTH-1:0] io_rsp_data_out,
|
||||
output wire io_rsp_ready_out
|
||||
);
|
||||
wire [NUM_REQS-1:0] valids;
|
||||
for (genvar i = 0; i < NUM_REQS; i++) begin
|
||||
assign valids[i] = (| io_req_valid_in[i]);
|
||||
end
|
||||
|
||||
wire [NUM_REQS-1:0][(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH))-1:0] data_in;
|
||||
for (genvar i = 0; i < NUM_REQS; i++) begin
|
||||
assign data_in[i] = {{io_req_valid_in[i], io_req_tag_in[i], REQS_BITS'(i)}, io_req_addr_in[i], io_req_rw_in[i], io_req_byteen_in[i], io_req_data_in[i]};
|
||||
end
|
||||
|
||||
wire [`NUM_THREADS-1:0] io_req_tmask_out;
|
||||
wire io_req_valid_out_unqual;
|
||||
|
||||
VX_stream_arbiter #(
|
||||
.NUM_REQS(NUM_REQS),
|
||||
.DATAW(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH)),
|
||||
.BUFFERED(NUM_REQS >= 4)
|
||||
) req_arb (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.valid_in (valids),
|
||||
.valid_out (io_req_valid_out_unqual),
|
||||
.data_in (data_in),
|
||||
.data_out ({io_req_tmask_out, io_req_tag_out, io_req_addr_out, io_req_rw_out, io_req_byteen_out, io_req_data_out}),
|
||||
.ready_in (io_req_ready_in),
|
||||
.ready_out (io_req_ready_out)
|
||||
);
|
||||
|
||||
assign io_req_valid_out = {`NUM_THREADS{io_req_valid_out_unqual}} & io_req_tmask_out;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
if (NUM_REQS > 1) begin
|
||||
|
||||
wire [NUM_REQS-1:0] valids;
|
||||
for (genvar i = 0; i < NUM_REQS; i++) begin
|
||||
assign valids[i] = (| io_req_valid_in[i]);
|
||||
end
|
||||
|
||||
wire [NUM_REQS-1:0][(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH))-1:0] data_in;
|
||||
for (genvar i = 0; i < NUM_REQS; i++) begin
|
||||
assign data_in[i] = {io_req_valid_in[i], {io_req_tag_in[i], REQS_BITS'(i)}, io_req_addr_in[i], io_req_rw_in[i], io_req_byteen_in[i], io_req_data_in[i]};
|
||||
end
|
||||
|
||||
wire [`NUM_THREADS-1:0] io_req_tmask_out;
|
||||
wire io_req_valid_out_unqual;
|
||||
|
||||
VX_stream_arbiter #(
|
||||
.NUM_REQS(NUM_REQS),
|
||||
.DATAW(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH)),
|
||||
.BUFFERED(NUM_REQS >= 4)
|
||||
) req_arb (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.valid_in (valids),
|
||||
.valid_out (io_req_valid_out_unqual),
|
||||
.data_in (data_in),
|
||||
.data_out ({io_req_tmask_out, io_req_tag_out, io_req_addr_out, io_req_rw_out, io_req_byteen_out, io_req_data_out}),
|
||||
.ready_in (io_req_ready_in),
|
||||
.ready_out (io_req_ready_out)
|
||||
);
|
||||
|
||||
assign io_req_valid_out = {`NUM_THREADS{io_req_valid_out_unqual}} & io_req_tmask_out;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
wire [REQS_BITS-1:0] rsp_sel = io_rsp_tag_out[REQS_BITS-1:0];
|
||||
|
||||
for (genvar i = 0; i < NUM_REQS; i++) begin
|
||||
@@ -92,6 +92,14 @@ module VX_io_arb #(
|
||||
`UNUSED_VAR (clk)
|
||||
`UNUSED_VAR (reset)
|
||||
|
||||
assign io_req_valid_out = io_req_valid_in;
|
||||
assign io_req_tag_out = io_req_tag_in;
|
||||
assign io_req_addr_out = io_req_addr_in;
|
||||
assign io_req_rw_out = io_req_rw_in;
|
||||
assign io_req_byteen_out = io_req_byteen_in;
|
||||
assign io_req_data_out = io_req_data_in;
|
||||
assign io_req_ready_in = io_req_ready_out;
|
||||
|
||||
assign io_rsp_valid_in = io_rsp_valid_out;
|
||||
assign io_rsp_tag_in = io_rsp_tag_out;
|
||||
assign io_rsp_data_in = io_rsp_data_out;
|
||||
|
||||
Reference in New Issue
Block a user