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scheduler optimization

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This commit is contained in:
Blaise Tine
2020-07-21 08:28:05 -07:00
parent fb44de8017
commit 0a56f96e69
1 changed files with 16 additions and 14 deletions
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30
hw/rtl/VX_scheduler.v
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@@ -16,29 +16,29 @@ module VX_scheduler #(
output wire schedule_delay, output wire schedule_delay,
output wire is_empty output wire is_empty
); );
localparam CTVW = `CLOG2(`NUM_WARPS * 32 + 1); localparam CTVW = `CLOG2(`NUM_WARPS * `NUM_REGS + 1);
reg [31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0]; reg [`NUM_REGS-1:0][`NUM_THREADS-1:0] rename_table [`NUM_WARPS-1:0];
reg [`NUM_REGS-1:0] busy_table[`NUM_WARPS-1:0];
reg [CTVW-1:0] count_valid; reg [CTVW-1:0] count_valid;
wire rs1_rename = (rename_table[decode_if.warp_num][decode_if.rs1] != 0); wire rs1_rename = busy_table[decode_if.warp_num][decode_if.rs1];
wire rs2_rename = (rename_table[decode_if.warp_num][decode_if.rs2] != 0); wire rs2_rename = busy_table[decode_if.warp_num][decode_if.rs2];
wire rd_rename = (rename_table[decode_if.warp_num][decode_if.rd ] != 0); wire rd_rename = busy_table[decode_if.warp_num][decode_if.rd];
wire rs1_rename_qual = (rs1_rename) && (decode_if.use_rs1); wire rs1_rename_qual = (rs1_rename) && (decode_if.use_rs1);
wire rs2_rename_qual = (rs2_rename) && (decode_if.use_rs2); wire rs2_rename_qual = (rs2_rename) && (decode_if.use_rs2);
wire rd_rename_qual = (rd_rename) && (decode_if.wb != 0); wire rd_rename_qual = (rd_rename) && (decode_if.wb != 0);
wire rename_valid = (| decode_if.valid) && (rs1_rename_qual || rs2_rename_qual || rd_rename_qual); wire rename_valid = (rs1_rename_qual || rs2_rename_qual || rd_rename_qual);
wire ex_stalled = (| decode_if.valid) wire ex_stalled = ((alu_busy && (decode_if.ex_type == `EX_ALU))
&& ((alu_busy && (decode_if.ex_type == `EX_ALU))
|| (lsu_busy && (decode_if.ex_type == `EX_LSU)) || (lsu_busy && (decode_if.ex_type == `EX_LSU))
|| (csr_busy && (decode_if.ex_type == `EX_CSR)) || (csr_busy && (decode_if.ex_type == `EX_CSR))
|| (mul_busy && (decode_if.ex_type == `EX_MUL)) || (mul_busy && (decode_if.ex_type == `EX_MUL))
|| (gpu_busy && (decode_if.ex_type == `EX_GPU))); || (gpu_busy && (decode_if.ex_type == `EX_GPU)));
wire stall = ex_stalled || rename_valid; wire stall = (ex_stalled || rename_valid) && (| decode_if.valid);
wire acquire_rd = (| decode_if.valid) && (decode_if.wb != 0) && ~stall; wire acquire_rd = (| decode_if.valid) && (decode_if.wb != 0) && ~stall;
@@ -49,23 +49,25 @@ module VX_scheduler #(
reg [CTVW-1:0] count_valid_next = (acquire_rd && !(release_rd && (0 == valid_wb_new_mask))) ? (count_valid + 1) : reg [CTVW-1:0] count_valid_next = (acquire_rd && !(release_rd && (0 == valid_wb_new_mask))) ? (count_valid + 1) :
(~acquire_rd && (release_rd && (0 == valid_wb_new_mask))) ? (count_valid - 1) : (~acquire_rd && (release_rd && (0 == valid_wb_new_mask))) ? (count_valid - 1) :
count_valid; count_valid;
integer i, w; always @(posedge clk) begin
always @(posedge clk) begin
if (reset) begin if (reset) begin
integer i, w;
for (w = 0; w < `NUM_WARPS; w++) begin for (w = 0; w < `NUM_WARPS; w++) begin
for (i = 0; i < 32; i++) begin for (i = 0; i < 32; i++) begin
rename_table[w][i] <= 0; rename_table[w][i] <= 0;
busy_table[w][i] <= 0;
end end
end end
count_valid <= 0; count_valid <= 0;
end else begin end else begin
if (acquire_rd) begin if (acquire_rd) begin
rename_table[decode_if.warp_num][decode_if.rd] <= decode_if.valid; rename_table[decode_if.warp_num][decode_if.rd] <= decode_if.valid;
busy_table[decode_if.warp_num][decode_if.rd] <= 1;
end end
if (release_rd) begin if (release_rd) begin
assert(rename_table[writeback_if.warp_num][writeback_if.rd] != 0); assert(rename_table[writeback_if.warp_num][writeback_if.rd] != 0);
rename_table[writeback_if.warp_num][writeback_if.rd] <= valid_wb_new_mask; rename_table[writeback_if.warp_num][writeback_if.rd] <= valid_wb_new_mask;
busy_table[writeback_if.warp_num][writeback_if.rd] <= (| valid_wb_new_mask);
end end
count_valid <= count_valid_next; count_valid <= count_valid_next;
end end