minor update
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@@ -23,7 +23,11 @@ module VX_gpr_fp_ctrl (
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always @(posedge clk) begin
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if (reset) begin
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read_rs1 <= 1;
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rs1_tmp_data <= 0;
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rs2_tmp_data <= 0;
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rs3_tmp_data <= 0;
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read_rs1 <= 1;
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rs3_wid <= 0;
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end else begin
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if (rs3_delay) begin
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read_rs1 <= 0;
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@@ -32,16 +36,18 @@ module VX_gpr_fp_ctrl (
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read_rs1 <= 1;
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end
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if (read_rs1) begin
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rs1_tmp_data <= rs1_data;
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end
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rs2_tmp_data <= rs2_data;
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rs3_tmp_data <= rs1_data;
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assert(read_rs1 || rs3_wid == gpr_read_if.wid);
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end
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end
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always @(posedge clk) begin
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if (read_rs1) begin
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rs1_tmp_data <= rs1_data;
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end
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rs2_tmp_data <= rs2_data;
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rs3_tmp_data <= rs1_data;
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end
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// outputs
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