wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

minor update

Browse Source
This commit is contained in:
Blaise Tine
2020-09-01 00:56:10 -07:00
parent 4e8b9fb296
commit 0a45a8beb3
11 changed files with 34 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
hw/rtl/VX_config.vh
View File

@@ -59,10 +59,6 @@
`define EXT_F_ENABLE
`endif
`ifndef FPNEW_DISABLE
`define FPNEW_ENABLE
`endif
// Device identification
`define VENDOR_ID 0
`define ARCHITECTURE_ID 0

2
hw/rtl/VX_fpu_unit.v
View File

@@ -56,7 +56,7 @@ module VX_fpu_unit #(
// can accept new request?
assign fpu_req_if.ready = ready_in && ~fpuq_full;
`ifndef FPNEW_ENABLE
`ifdef FPU_FAST
VX_fp_fpga #(
.TAGW (FPUQ_BITS)

18
hw/rtl/VX_gpr_fp_ctrl.v
View File

@@ -23,7 +23,11 @@ module VX_gpr_fp_ctrl (
always @(posedge clk) begin
if (reset) begin
read_rs1 <= 1;
rs1_tmp_data <= 0;
rs2_tmp_data <= 0;
rs3_tmp_data <= 0;
read_rs1 <= 1;
rs3_wid <= 0;
end else begin
if (rs3_delay) begin
read_rs1 <= 0;
@@ -32,16 +36,18 @@ module VX_gpr_fp_ctrl (
read_rs1 <= 1;
end
if (read_rs1) begin
rs1_tmp_data <= rs1_data;
end
rs2_tmp_data <= rs2_data;
rs3_tmp_data <= rs1_data;
assert(read_rs1 || rs3_wid == gpr_read_if.wid);
end
end
always @(posedge clk) begin
if (read_rs1) begin
rs1_tmp_data <= rs1_data;
end
rs2_tmp_data <= rs2_data;
rs3_tmp_data <= rs1_data;
end
// outputs

14
hw/rtl/fp_cores/VX_fp_madd.v
View File

@@ -51,9 +51,9 @@ module VX_fp_madd #(
.chainin_invalid(),
.chainin_underflow(),
.chainin_inexact(),
.ax(),
.ax(dataa[i]),
.ay(datab[i]),
.az(dataa[i]),
.az(),
.clk({2'b00,clk}),
.ena({2'b11,~stall}),
.aclr(2'b00),
@@ -75,12 +75,12 @@ module VX_fp_madd #(
defparam mac_fp_add.adder_subtract = "false";
defparam mac_fp_add.ax_clock = "0";
defparam mac_fp_add.ay_clock = "0";
defparam mac_fp_add.az_clock = "0";
defparam mac_fp_add.az_clock = "none";
defparam mac_fp_add.output_clock = "0";
defparam mac_fp_add.accumulate_clock = "none";
defparam mac_fp_add.ax_chainin_pl_clock = "0";
defparam mac_fp_add.ax_chainin_pl_clock = "none";
defparam mac_fp_add.accum_pipeline_clock = "none";
defparam mac_fp_add.mult_pipeline_clock = "0";
defparam mac_fp_add.mult_pipeline_clock = "none";
defparam mac_fp_add.adder_input_clock = "0";
defparam mac_fp_add.accum_adder_clock = "none";
@@ -91,9 +91,9 @@ module VX_fp_madd #(
.chainin_invalid(),
.chainin_underflow(),
.chainin_inexact(),
.ax(),
.ax(dataa[i]),
.ay(datab[i]),
.az(dataa[i]),
.az(),
.clk({2'b00,clk}),
.ena({2'b11,~stall}),
.aclr(2'b00),

2
hw/rtl/fp_cores/VX_fp_nmadd.v
View File

@@ -52,7 +52,7 @@ module VX_fp_nmadd #(
.ay(datab[i]),
.az(dataa[i]),
.clk({2'b00,clk}),
.ena({2'b11,~stall),
.ena({2'b11,~stall}),
.aclr(2'b00),
.chainin(),
// outputs