From 0909ad320120882b6e795e86eeade69e4dc2636a Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 20 Mar 2021 21:57:06 -0400 Subject: [PATCH] minor update --- hw/rtl/cache/VX_bank.v | 6 +++--- hw/rtl/cache/VX_cache_define.vh | 2 ++ hw/rtl/cache/VX_shared_mem.v | 2 +- hw/rtl/tex_unit/VX_tex_addr_gen.v | 22 +++++++++++----------- 4 files changed, 17 insertions(+), 15 deletions(-) diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index eda0bfb1..0d2bea29 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -211,7 +211,7 @@ module VX_bank #( `ifdef DBG_CACHE_REQ_INFO if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin - assign {debug_pc_sel, debug_wid_sel} = mshr_pop_unqual ? mshr_tag[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS] : creq_tag[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS]; + assign {debug_pc_sel, debug_wid_sel} = mshr_pop_unqual ? mshr_tag[`CACHE_REQ_INFO_RNG] : creq_tag[`CACHE_REQ_INFO_RNG]; end else begin assign {debug_pc_sel, debug_wid_sel} = 0; end @@ -273,7 +273,7 @@ module VX_bank #( `ifdef DBG_CACHE_REQ_INFO if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin - assign {debug_pc_st0, debug_wid_st0} = tag_st0[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS]; + assign {debug_pc_st0, debug_wid_st0} = tag_st0[`CACHE_REQ_INFO_RNG]; end else begin assign {debug_pc_st0, debug_wid_st0} = 0; end @@ -339,7 +339,7 @@ module VX_bank #( `ifdef DBG_CACHE_REQ_INFO if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin - assign {debug_pc_st1, debug_wid_st1} = tag_st1[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS]; + assign {debug_pc_st1, debug_wid_st1} = tag_st1[`CACHE_REQ_INFO_RNG]; end else begin assign {debug_pc_st1, debug_wid_st1} = 0; end diff --git a/hw/rtl/cache/VX_cache_define.vh b/hw/rtl/cache/VX_cache_define.vh index e205d7ad..3cd802a1 100644 --- a/hw/rtl/cache/VX_cache_define.vh +++ b/hw/rtl/cache/VX_cache_define.vh @@ -51,6 +51,8 @@ `define LINE_TAG_ADDR(x) x[`LINE_ADDR_WIDTH-1 : `LINE_SELECT_BITS] +`define CACHE_REQ_INFO_RNG CORE_TAG_WIDTH-1:(CORE_TAG_WIDTH-`NW_BITS-32) + /////////////////////////////////////////////////////////////////////////////// `define CORE_REQ_TAG_COUNT ((CORE_TAG_ID_BITS != 0) ? 1 : NUM_REQS) diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index 7d500733..5241f9d4 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -193,7 +193,7 @@ module VX_shared_mem #( `ifdef DBG_CACHE_REQ_INFO if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin - assign {debug_pc_st0, debug_wid_st0} = core_rsp_tag_in[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS]; + assign {debug_pc_st0, debug_wid_st0} = core_rsp_tag_in[`CACHE_REQ_INFO_RNG]; end else begin assign {debug_pc_st0, debug_wid_st0} = 0; end diff --git a/hw/rtl/tex_unit/VX_tex_addr_gen.v b/hw/rtl/tex_unit/VX_tex_addr_gen.v index 64b8d1b7..f6eba173 100644 --- a/hw/rtl/tex_unit/VX_tex_addr_gen.v +++ b/hw/rtl/tex_unit/VX_tex_addr_gen.v @@ -45,8 +45,8 @@ module VX_tex_addr_gen #( `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (lod) - wire [`NUM_THREADS-1:0][1:0][`FIXED_FRAC-1:0] u; - wire [`NUM_THREADS-1:0][1:0][`FIXED_FRAC-1:0] v; + wire [1:0][`NUM_THREADS-1:0][`FIXED_FRAC-1:0] u; + wire [1:0][`NUM_THREADS-1:0][`FIXED_FRAC-1:0] v; // addressing mode @@ -65,7 +65,7 @@ module VX_tex_addr_gen #( ) tex_wrap_u0 ( .wrap_i (wrap_u), .coord_i (fu[0]), - .coord_o (u[i][0]) + .coord_o (u[0][i]) ); VX_tex_wrap #( @@ -73,7 +73,7 @@ module VX_tex_addr_gen #( ) tex_wrap_v0 ( .wrap_i (wrap_v), .coord_i (fv[0]), - .coord_o (v[i][0]) + .coord_o (v[0][i]) ); VX_tex_wrap #( @@ -81,7 +81,7 @@ module VX_tex_addr_gen #( ) tex_wrap_u1 ( .wrap_i (wrap_u), .coord_i (fu[1]), - .coord_o (u[i][1]) + .coord_o (u[1][i]) ); VX_tex_wrap #( @@ -89,7 +89,7 @@ module VX_tex_addr_gen #( ) tex_wrap_v1 ( .wrap_i (wrap_v), .coord_i (fv[1]), - .coord_o (v[i][1]) + .coord_o (v[1][i]) ); end @@ -102,10 +102,10 @@ module VX_tex_addr_gen #( wire [`FIXED_FRAC-1:0] x [1:0]; wire [`FIXED_FRAC-1:0] y [1:0]; - assign x[0] = u[i][0] >> ((`FIXED_FRAC) - log2_width); - assign x[1] = u[i][1] >> ((`FIXED_FRAC) - log2_width); - assign y[0] = v[i][0] >> ((`FIXED_FRAC) - log2_height); - assign y[1] = v[i][1] >> ((`FIXED_FRAC) - log2_height); + assign x[0] = u[0][i] >> ((`FIXED_FRAC) - log2_width); + assign x[1] = u[1][i] >> ((`FIXED_FRAC) - log2_width); + assign y[0] = v[0][i] >> ((`FIXED_FRAC) - log2_height); + assign y[1] = v[1][i] >> ((`FIXED_FRAC) - log2_height); assign addr[i][0] = base_addr + (32'(x[0]) + (32'(y[0]) << log2_width)) << log2_stride; assign addr[i][1] = base_addr + (32'(x[1]) + (32'(y[0]) << log2_width)) << log2_stride; @@ -116,7 +116,7 @@ module VX_tex_addr_gen #( wire stall_out = mem_req_valid && ~mem_req_ready; VX_pipe_register #( - .DATAW (1 + `NUM_THREADS + `TEX_FILTER_BITS + REQ_TAG_WIDTH + (`NUM_THREADS * 4 * 32) + (`NUM_THREADS * `FIXED_FRAC)), + .DATAW (1 + `NUM_THREADS + `TEX_FILTER_BITS + REQ_TAG_WIDTH + (`NUM_THREADS * 4 * 32) + (2*`NUM_THREADS * `FIXED_FRAC)), .RESETW (1) ) pipe_reg ( .clk (clk),