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code refactoring

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This commit is contained in:
Blaise Tine
2020-03-26 03:20:46 -04:00
parent bf3d1fb5a2
commit 07c52d8729
4 changed files with 84 additions and 104 deletions
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2
rtl/VX_define.v
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@@ -127,7 +127,7 @@
`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
//`define SINGLE_CORE_BENCH `define SINGLE_CORE_BENCH
`define GLOBAL_BLOCK_SIZE_BYTES 16 `define GLOBAL_BLOCK_SIZE_BYTES 16

1
rtl/VX_define_synth.v
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@@ -12,7 +12,6 @@
// L2 Cache size // L2 Cache size
`define LLCACHE_SIZE_BYTES 8192 `define LLCACHE_SIZE_BYTES 8192
// `define QUEUE_FORCE_MLAB 1 // `define QUEUE_FORCE_MLAB 1
// Use l3 cache (required for cluster behavior) // Use l3 cache (required for cluster behavior)

168
rtl/Vortex.v
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@@ -4,108 +4,90 @@
module Vortex module Vortex
#( #(
parameter CORE_ID = 0 parameter CORE_ID = 0
) ) (
( `ifdef SINGLE_CORE_BENCH
`ifdef SINGLE_CORE_BENCH
input wire clk,
input wire reset,
// IO
output wire io_valid,
output wire[31:0] io_data,
// DRAM Dcache Req // Clock
output wire dram_req, input wire clk,
output wire dram_req_write, input wire reset,
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG],
output wire [31:0] dram_expected_lat,
// DRAM Dcache Res // IO
output wire dram_fill_accept, output wire io_valid,
input wire dram_fill_rsp, output wire[31:0] io_data,
input wire [31:0] dram_fill_rsp_addr,
input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], // DRAM Dcache Req
output wire dram_req,
output wire dram_req_write,
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG],
output wire [31:0] dram_expected_lat,
// DRAM Dcache Res
output wire dram_fill_accept,
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
// LLC Snooping
input wire snp_req,
input wire [31:0] snp_req_addr,
output wire snp_req_delay,
output wire out_ebreak
`else
input wire clk,
input wire reset,
// IO
output wire io_valid,
output wire[31:0] io_data,
// DRAM Dcache Req
output wire dram_req,
output wire dram_req_write,
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire [31:0] dram_expected_lat,
// DRAM Dcache Res
output wire dram_fill_accept,
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
// DRAM Icache Req // DRAM Icache Req
output wire I_dram_req, output wire I_dram_req,
output wire I_dram_req_write, output wire I_dram_req_write,
output wire I_dram_req_read, output wire I_dram_req_read,
output wire [31:0] I_dram_req_addr, output wire [31:0] I_dram_req_addr,
output wire [31:0] I_dram_req_size, output wire [31:0] I_dram_req_size,
output wire [31:0] I_dram_req_data[`IBANK_LINE_SIZE_RNG], output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
output wire [31:0] I_dram_expected_lat, output wire [31:0] I_dram_expected_lat,
// DRAM Icache Res // DRAM Icache Res
output wire I_dram_fill_accept, output wire I_dram_fill_accept,
input wire I_dram_fill_rsp, input wire I_dram_fill_rsp,
input wire [31:0] I_dram_fill_rsp_addr, input wire [31:0] I_dram_fill_rsp_addr,
input wire [31:0] I_dram_fill_rsp_data[`IBANK_LINE_SIZE_RNG], input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
input wire snp_req,
input wire [31:0] snp_req_addr,
output wire snp_req_delay,
input wire I_snp_req,
input wire [31:0] I_snp_req_addr,
output wire I_snp_req_delay,
output wire out_ebreak
`else
input wire clk,
input wire reset,
// IO
output wire io_valid,
output wire[31:0] io_data,
// DRAM Dcache Req
output wire dram_req,
output wire dram_req_write,
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire [31:0] dram_expected_lat,
// DRAM Dcache Res
output wire dram_fill_accept,
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
// DRAM Icache Req input wire snp_req,
output wire I_dram_req, input wire [31:0] snp_req_addr,
output wire I_dram_req_write, output wire snp_req_delay,
output wire I_dram_req_read,
output wire [31:0] I_dram_req_addr,
output wire [31:0] I_dram_req_size,
output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
output wire [31:0] I_dram_expected_lat,
// DRAM Icache Res input wire I_snp_req,
output wire I_dram_fill_accept, input wire [31:0] I_snp_req_addr,
input wire I_dram_fill_rsp, output wire I_snp_req_delay,
input wire [31:0] I_dram_fill_rsp_addr,
input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
output wire out_ebreak
input wire snp_req, `endif
input wire [31:0] snp_req_addr, );
output wire snp_req_delay,
input wire I_snp_req,
input wire [31:0] I_snp_req_addr,
output wire I_snp_req_delay,
output wire out_ebreak
`endif
);
wire scheduler_empty; wire scheduler_empty;
wire out_ebreak_unqual; wire out_ebreak_unqual;

13
rtl/Vortex_SOC.v
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@@ -3,9 +3,9 @@
module Vortex_SOC ( module Vortex_SOC (
// System Clock // Clock
input wire clk, input wire clk,
input wire reset, input wire reset,
// IO // IO
output wire io_valid[`NUMBER_CORES-1:0], output wire io_valid[`NUMBER_CORES-1:0],
@@ -13,7 +13,7 @@ module Vortex_SOC (
output wire[31:0] number_cores, output wire[31:0] number_cores,
// DRAM Dcache Req // DRAM Req
output wire out_dram_req, output wire out_dram_req,
output wire out_dram_req_write, output wire out_dram_req_write,
output wire out_dram_req_read, output wire out_dram_req_read,
@@ -22,12 +22,13 @@ module Vortex_SOC (
output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG], output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG],
output wire [31:0] out_dram_expected_lat, output wire [31:0] out_dram_expected_lat,
// DRAM Dcache Res // DRAM Res
output wire out_dram_fill_accept, output wire out_dram_fill_accept,
input wire out_dram_fill_rsp, input wire out_dram_fill_rsp,
input wire [31:0] out_dram_fill_rsp_addr, input wire [31:0] out_dram_fill_rsp_addr,
input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
// LLC Snooping
input wire llc_snp_req, input wire llc_snp_req,
input wire llc_snp_req_addr, input wire llc_snp_req_addr,
output wire llc_snp_req_delay, output wire llc_snp_req_delay,
@@ -605,8 +606,6 @@ module Vortex_SOC (
// end // end
// endgenerate // endgenerate
// //
genvar l2c_curr_core; genvar l2c_curr_core;
generate generate