code refactoring

rtl/VX_define.v

@@ -127,7 +127,7 @@
 
 `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
 
-//`define SINGLE_CORE_BENCH
+`define SINGLE_CORE_BENCH
 
 `define GLOBAL_BLOCK_SIZE_BYTES 16
 

rtl/VX_define_synth.v

@@ -12,7 +12,6 @@
 // L2 Cache size
 `define LLCACHE_SIZE_BYTES 8192
 
-
 // `define QUEUE_FORCE_MLAB 1
 
 // Use l3 cache (required for cluster behavior)

rtl/Vortex.v

@@ -4,11 +4,13 @@
 module Vortex
 	#( 
 		parameter CORE_ID = 0
-	)
+	) (		
-	(
+`ifdef SINGLE_CORE_BENCH
-		`ifdef SINGLE_CORE_BENCH
+
+	// Clock
 	input  wire           	clk,
 	input  wire           	reset,
+
 	// IO
 	output wire        		io_valid,
 	output wire[31:0]  		io_data,
@@ -28,33 +30,14 @@ module Vortex
 	input  wire [31:0]      dram_fill_rsp_addr,
 	input  wire [31:0]      dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
 
-
+	// LLC Snooping
-			// DRAM Icache Req
-		    output wire                              I_dram_req,
-		    output wire                              I_dram_req_write,
-		    output wire                              I_dram_req_read,
-		    output wire [31:0]                       I_dram_req_addr,
-		    output wire [31:0]                       I_dram_req_size,
-		    output wire [31:0]                       I_dram_req_data[`IBANK_LINE_SIZE_RNG],
-		    output wire [31:0]                       I_dram_expected_lat,
-
-			// DRAM Icache Res
-			output wire                              I_dram_fill_accept,
-		    input  wire                              I_dram_fill_rsp,
-		    input  wire [31:0]                       I_dram_fill_rsp_addr,
-		    input  wire [31:0]                       I_dram_fill_rsp_data[`IBANK_LINE_SIZE_RNG],
-
 	input  wire             snp_req,
 	input  wire [31:0]      snp_req_addr,
 	output wire             snp_req_delay,
 
-		    input  wire                              I_snp_req,
-		    input  wire [31:0]                       I_snp_req_addr,
-		    output wire                              I_snp_req_delay,
-
 	output wire             out_ebreak
 
-		 `else 
+`else 
 
 	input  wire           					 clk,
 	input  wire           					 reset,
@@ -102,10 +85,9 @@ module Vortex
 	input  wire [31:0]                       I_snp_req_addr,
 	output wire                              I_snp_req_delay,
 
-
 	output wire        						 out_ebreak
-		`endif
+`endif
-	);
+);
 
 	wire scheduler_empty;
 	wire out_ebreak_unqual;

rtl/Vortex_SOC.v

@@ -3,7 +3,7 @@
 
 module Vortex_SOC (
 
-    // System Clock
+    // Clock
     input  wire             clk,
     input  wire             reset,
 
@@ -13,7 +13,7 @@ module Vortex_SOC (
 
     output wire[31:0]       number_cores,
 
-    // DRAM Dcache Req
+    // DRAM Req
     output wire             out_dram_req,
     output wire             out_dram_req_write,
     output wire             out_dram_req_read,
@@ -22,12 +22,13 @@ module Vortex_SOC (
     output wire [31:0]      out_dram_req_data[`DBANK_LINE_SIZE_RNG],
     output wire [31:0]      out_dram_expected_lat,
 
-    // DRAM Dcache Res
+    // DRAM Res
     output wire             out_dram_fill_accept,
     input  wire             out_dram_fill_rsp,
     input  wire [31:0]      out_dram_fill_rsp_addr,
     input  wire [31:0]      out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
 
+    // LLC Snooping
     input  wire             llc_snp_req,
     input  wire             llc_snp_req_addr,
     output wire             llc_snp_req_delay,
@@ -605,8 +606,6 @@ module Vortex_SOC (
     //     end
     // endgenerate
 
-
-
     // 
     genvar l2c_curr_core;
     generate