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minor update

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This commit is contained in:
Blaise Tine
2021-02-12 08:52:06 -08:00
parent ab63ac9e5d
commit 073964fdf7
8 changed files with 59 additions and 59 deletions
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2
hw/rtl/VX_config.vh
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@@ -313,7 +313,7 @@
// Miss Handling Register Size
`ifndef DMSHR_SIZE
`define DMSHR_SIZE `LSUQ_SIZE
`define DMSHR_SIZE (`LSUQ_SIZE / 2)
`endif
// DRAM Request Queue Size

3
hw/rtl/VX_csr_arb.v
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@@ -66,7 +66,8 @@ module VX_csr_arb #(
VX_stream_arbiter #(
.NUM_REQS (NUM_REQS),
.DATAW (RSP_DATAW),
.BUFFERED (BUFFERED_RSP)
.BUFFERED (BUFFERED_RSP),
.TYPE ("X") // fixed arbitration
) rsp_arb (
.clk (clk),
.reset (reset),

16
hw/rtl/fp_cores/VX_fp_div.v
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@@ -29,7 +29,17 @@ module VX_fp_div #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
for (genvar i = 0; i < LANES; i++) begin
for (genvar i = 0; i < LANES; i++) begin
wire fdiv_reset;
VX_reset_relay #(
.NUM_NODES(1)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fdiv_reset)
);
`ifdef VERILATOR
reg [31:0] r;
fflags_t f;
@@ -45,7 +55,7 @@ module VX_fp_div #(
.RESETW (1)
) shift_req_dpi (
.clk (clk),
.reset (reset),
.reset (fdiv_reset),
.enable (enable),
.data_in (r),
.data_out (result[i])
@@ -53,7 +63,7 @@ module VX_fp_div #(
`else
acl_fdiv fdiv (
.clk (clk),
.areset (reset),
.areset (fdiv_reset),
.en (enable),
.a (dataa[i]),
.b (datab[i]),

16
hw/rtl/fp_cores/VX_fp_sqrt.v
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@@ -28,7 +28,17 @@ module VX_fp_sqrt #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
for (genvar i = 0; i < LANES; i++) begin
for (genvar i = 0; i < LANES; i++) begin
wire fsqrt_reset;
VX_reset_relay #(
.NUM_NODES(1)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fsqrt_reset)
);
`ifdef VERILATOR
reg [31:0] r;
fflags_t f;
@@ -44,7 +54,7 @@ module VX_fp_sqrt #(
.RESETW (1)
) shift_req_dpi (
.clk (clk),
.reset (reset),
.reset (fsqrt_reset),
.enable (enable),
.data_in (r),
.data_out (result[i])
@@ -52,7 +62,7 @@ module VX_fp_sqrt #(
`else
acl_fsqrt fsqrt (
.clk (clk),
.areset (reset),
.areset (fsqrt_reset),
.en (enable),
.a (dataa[i]),
.q (result[i])

2
hw/rtl/libs/VX_stream_arbiter.v
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@@ -16,7 +16,7 @@ module VX_stream_arbiter #(
output wire valid_out,
output wire [DATAW-1:0] data_out,
input wire ready_out
);
);
localparam LOG_NUM_REQS = $clog2(NUM_REQS);