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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 06:47:24 -04:00
parent 5671b08a5e
commit 07135263f5
22 changed files with 334 additions and 474 deletions
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2
hw/rtl/interfaces/VX_gpu_dcache_dram_req_if.v
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@@ -12,7 +12,7 @@ interface VX_gpu_dcache_dram_req_if #(
wire dram_req_read;
wire [31:0] dram_req_addr;
wire [BANK_LINE_WORDS-1:0][31:0] dram_req_data;
wire dram_req_full;
wire dram_req_ready;
wire dram_rsp_ready;

12
hw/rtl/interfaces/VX_gpu_dcache_req_if.v
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@@ -7,21 +7,21 @@ interface VX_gpu_dcache_req_if #(
parameter NUM_REQUESTS = 32
) ();
// Core Request
// Core request
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][31:0] core_req_writedata;
wire [NUM_REQUESTS-1:0][2:0] core_req_mem_read;
wire [NUM_REQUESTS-1:0][2:0] core_req_mem_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][31:0] core_req_writedata;
// Core request Meta data
wire [4:0] core_req_rd;
wire [NUM_REQUESTS-1:0][1:0] core_req_wb;
wire [`NW_BITS-1:0] core_req_warp_num;
wire [31:0] core_req_pc;
// Can't WB
wire core_no_wb_slot;
wire core_no_wb_slot;
endinterface
`endif

13
hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
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@@ -7,18 +7,19 @@ interface VX_gpu_dcache_rsp_if #(
parameter NUM_REQUESTS = 32
) ();
// Cache WB
// Core response
wire [NUM_REQUESTS-1:0] core_wb_valid;
`IGNORE_WARNINGS_BEGIN
wire [4:0] core_wb_req_rd;
wire [1:0] core_wb_req_wb;
`IGNORE_WARNINGS_END
wire [`NW_BITS-1:0] core_wb_warp_num;
`IGNORE_WARNINGS_END
wire [NUM_REQUESTS-1:0][31:0] core_wb_pc;
wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata;
wire [NUM_REQUESTS-1:0][31:0] core_wb_pc;
// Core response meta data
wire [`NW_BITS-1:0] core_wb_warp_num;
// Cache Full
wire delay_req;
wire core_req_ready;
endinterface