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RTL code refactoring

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Blaise Tine
2020-04-20 06:47:24 -04:00
parent 5671b08a5e
commit 07135263f5
22 changed files with 334 additions and 474 deletions
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4
hw/rtl/generic_cache/VX_bank.v
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@@ -48,7 +48,7 @@ module VX_bank #(
input wire reset,
// Input Core Request
input wire delay_req,
input wire req_ready,
input wire [NUM_REQUESTS-1:0] bank_valids,
input wire [NUM_REQUESTS-1:0][31:0] bank_addr,
input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata,
@@ -168,7 +168,7 @@ module VX_bank #(
wire [2:0] reqq_req_mem_write_st0;
wire [31:0] reqq_req_pc_st0;
assign reqq_push = !delay_req && (|bank_valids);
assign reqq_push = req_ready && (|bank_valids);
VX_cache_req_queue #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),