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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 06:47:24 -04:00
parent 5671b08a5e
commit 07135263f5
22 changed files with 334 additions and 474 deletions
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69
hw/rtl/Vortex_Socket.v
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@@ -2,21 +2,20 @@
`include "VX_cache_config.vh"
module Vortex_Socket (
// Clock
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// IO
output wire io_valid[`NUM_CORES-1:0],
output wire[31:0] io_data [`NUM_CORES-1:0],
output wire io_valid[`NUM_CORES-1:0],
output wire[31:0] io_data [`NUM_CORES-1:0],
// DRAM Req
output wire dram_req_read,
output wire dram_req_write,
output wire [31:0] dram_req_addr,
output wire [`DBANK_LINE_SIZE-1:0] dram_req_data,
input wire dram_req_full,
input wire dram_req_ready,
// DRAM Rsp
input wire dram_rsp_valid,
@@ -25,11 +24,11 @@ module Vortex_Socket (
output wire dram_rsp_ready,
// LLC Snooping
input wire llc_snp_req_valid,
input wire[31:0] llc_snp_req_addr,
output wire llc_snp_req_full,
input wire llc_snp_req_valid,
input wire[31:0] llc_snp_req_addr,
output wire llc_snp_req_full,
output wire out_ebreak
output wire out_ebreak
);
if (`NUM_CLUSTERS == 1) begin
@@ -53,7 +52,7 @@ module Vortex_Socket (
.dram_req_write (dram_req_write),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_full (dram_req_full),
.dram_req_ready (dram_req_ready),
.dram_rsp_valid (dram_rsp_valid),
.dram_rsp_addr (dram_rsp_addr),
@@ -85,7 +84,7 @@ module Vortex_Socket (
wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_req_data;
wire[31:0] per_cluster_dram_req_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0];
wire l3c_core_req_full;
wire l3c_core_req_ready;
// // DRAM Dcache Rsp
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready;
@@ -113,7 +112,9 @@ module Vortex_Socket (
genvar curr_cluster;
for (curr_cluster = 0; curr_cluster < `NUM_CLUSTERS; curr_cluster=curr_cluster+1) begin
Vortex_Cluster #(.CLUSTER_ID(curr_cluster)) Vortex_Cluster(
Vortex_Cluster #(
.CLUSTER_ID(curr_cluster)
) Vortex_Cluster(
.clk (clk),
.reset (reset),
.io_valid (per_cluster_io_valid [curr_cluster]),
@@ -123,7 +124,7 @@ module Vortex_Socket (
.dram_req_read (per_cluster_dram_req_read [curr_cluster]),
.dram_req_addr (per_cluster_dram_req_addr [curr_cluster]),
.dram_req_data (per_cluster_dram_req_data_up [curr_cluster]),
.dram_req_full (l3c_core_req_full),
.dram_req_ready (l3c_core_req_ready),
.dram_rsp_valid (per_cluster_dram_rsp_valid [curr_cluster]),
.dram_rsp_addr (per_cluster_dram_rsp_addr [curr_cluster]),
@@ -139,6 +140,7 @@ module Vortex_Socket (
end
//////////////////// L3 Cache ////////////////////
wire[`L3NUM_REQUESTS-1:0] l3c_core_req_valid;
wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_write;
wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_read;
@@ -161,25 +163,24 @@ module Vortex_Socket (
assign dram_rsp_data_port[llb_index] = dram_rsp_data[llb_index];
end
//
genvar l3c_curr_cluster;
for (l3c_curr_cluster = 0; l3c_curr_cluster < `L3NUM_REQUESTS; l3c_curr_cluster=l3c_curr_cluster+1) begin
// Core Request
assign l3c_core_req_valid [l3c_curr_cluster] = per_cluster_dram_req_valid[l3c_curr_cluster];
assign l3c_core_req_mem_read [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? `LW_MEM_READ : `NO_MEM_READ;
assign l3c_core_req_mem_write [l3c_curr_cluster] = per_cluster_dram_req_write[l3c_curr_cluster] ? `SW_MEM_WRITE : `NO_MEM_WRITE;
assign l3c_core_req_wb [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? 1 : 0;
assign l3c_core_req_addr [l3c_curr_cluster] = per_cluster_dram_req_addr [l3c_curr_cluster];
assign l3c_core_req_data [l3c_curr_cluster] = per_cluster_dram_req_data [l3c_curr_cluster];
for (l3c_curr_cluster = 0; l3c_curr_cluster < `L3NUM_REQUESTS; l3c_curr_cluster=l3c_curr_cluster+1) begin
// Core Request
assign l3c_core_req_valid [l3c_curr_cluster] = per_cluster_dram_req_valid[l3c_curr_cluster];
assign l3c_core_req_mem_read [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? `LW_MEM_READ : `NO_MEM_READ;
assign l3c_core_req_mem_write [l3c_curr_cluster] = per_cluster_dram_req_write[l3c_curr_cluster] ? `SW_MEM_WRITE : `NO_MEM_WRITE;
assign l3c_core_req_wb [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? 1 : 0;
assign l3c_core_req_addr [l3c_curr_cluster] = per_cluster_dram_req_addr [l3c_curr_cluster];
assign l3c_core_req_data [l3c_curr_cluster] = per_cluster_dram_req_data [l3c_curr_cluster];
// Core can't accept Response
assign l3c_core_no_wb_slot [l3c_curr_cluster] = ~per_cluster_dram_rsp_ready[l3c_curr_cluster];
// Core can't accept Response
assign l3c_core_no_wb_slot [l3c_curr_cluster] = ~per_cluster_dram_rsp_ready[l3c_curr_cluster];
// Cache Fill Response
assign per_cluster_dram_rsp_valid [l3c_curr_cluster] = l3c_wb [l3c_curr_cluster];
assign per_cluster_dram_rsp_data [l3c_curr_cluster] = l3c_wb_data [l3c_curr_cluster];
assign per_cluster_dram_rsp_addr [l3c_curr_cluster] = l3c_wb_addr [l3c_curr_cluster];
end
// Cache Fill Response
assign per_cluster_dram_rsp_valid [l3c_curr_cluster] = l3c_wb [l3c_curr_cluster];
assign per_cluster_dram_rsp_data [l3c_curr_cluster] = l3c_wb_data [l3c_curr_cluster];
assign per_cluster_dram_rsp_addr [l3c_curr_cluster] = l3c_wb_addr [l3c_curr_cluster];
end
VX_cache #(
.CACHE_SIZE_BYTES (`L3CACHE_SIZE_BYTES),
@@ -203,8 +204,8 @@ module Vortex_Socket (
.FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`L3SIMULATED_DRAM_LATENCY_CYCLES)
) gpu_l3cache (
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
// Core Req (DRAM Fills/WB) To L2 Request
.core_req_valid (l3c_core_req_valid),
@@ -218,7 +219,7 @@ module Vortex_Socket (
.core_req_pc (0),
// L2 can't accept Core Request
.delay_req (l3c_core_req_full),
.core_req_ready (l3c_core_req_ready),
// Core can't accept L2 Request
.core_no_wb_slot (|l3c_core_no_wb_slot),
@@ -247,7 +248,7 @@ module Vortex_Socket (
.dram_req_read (dram_req_read),
.dram_req_addr (dram_req_addr),
.dram_req_data ({dram_req_data_port}),
.dram_req_full (dram_req_full),
.dram_req_ready (dram_req_ready),
// Snoop Request
.snp_req_valid (llc_snp_req_valid),