RTL code refactoring

hw/rtl/VX_lsu.v

@@ -59,7 +59,7 @@ module VX_lsu (
 	assign dcache_req_if.core_no_wb_slot     = no_slot_mem;	
 
 	// Cache can't accept request
-	assign out_delay = dcache_rsp_if.delay_req;
+	assign out_delay = ~dcache_rsp_if.core_req_ready;
 
 	// Core Response
 	assign mem_wb_if.rd          = dcache_rsp_if.core_wb_req_rd;